CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.16 System Bus Registers
TS0 Embedded
The offline framer examines TXDATA to align TX timebase to the
embedded FAS pattern. If MFAS is also enabled [TFRAME; addr
070], transmit online framer examines TXDATA to align TX timebase
to the embedded MFAS pattern. While EMBED is active, TXDATA
output is monitored, and transmit frame errors are reported in ISR0
[addr 00B]. Embedded TS0 supports E1 overhead bypass options for
applications where TSLIP buffer is enabled.
G.802 Embedded
Automatically supports ITU–T Recommendation G.802, which
defines frame format conversion between T1 and E1 line rates. This is
accomplished by locating T1 F-bits in Bit 1 of Time Slot 26 of each
system bus frame. G.802 embedded mode is applicable for system
buses that are 1x, 2x, or 4x multiples of E1 line rate. Full
implementation of G.802 also requires the processor to program TS0,
TS16, and TS26–TS31 as unassigned system bus time slots [SBCn;
addr 0E0–0FF].
SBI[3:0]
System Bus Interface Mode—Defines transmit and receive system bus data format. System
buses operate in one of nine basic formats which differ in the number of total available data
time slots and the associated system bus clock rate. If the total time slots are a multiple of 32,
SBI also defines which bus group of 32 byte-interleaved time slots are assigned to the
respective device.
SBI[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
Mode
128A
128B
128C
128D
64A
64B
Clock (Kbps)
8192
Total Time Slots
Bus Group
Group 0
Group 1
Group 2
Group 3
Group 0
Group 1
—
128
128
8192
8192
128
8192
128
4096
64
4096
64
32
2048
32
24+F
24
1544
24 + F-bit
24
—
1536
—
100054E
Conexant
3-95
CONEXANT [ CONEXANT SYSTEMS, INC ]
