3.0 Registers
CX28394/28395/28398
3.16 System Bus Registers
Quad/x16/Octal—T1/E1/J1 Framers
0D1—Receive System Bus Configuration (RSB_CR)
7
6
5
4
3
2
1
0
BUS_RSB
SIG_OFF
RPCM_NEG
RSYN_NEG
BUS_FRZ
RSB_CTR
RSBI[1]
RSBI[0]
BUS_RSB
Enable Bussed RSB Outputs—Applicable only if the system bus outputs are controlled by SBI
timebases [SBI_OE = 1; addr 0D0]. When BUS_RSB is active, RPCMO, RSIGO, and RINDO
outputs from multiple devices are allowed to share common receive system bus connections.
Unused time slots are three-stated during those bus groups that are not selected by SBI mode
[addr 0D0]. Otherwise, unused time slots repeat their output data value for all bus groups.
0 = RSB time slot value repeated for all bus groups
1 = three-state RSB outputs during unused bus groups
SIG_OFF
Inhibit RPCMO Signaling Reinsertion—Disables insertion of ABCD signaling for all time
slots on the receive system bus PCM output (RPCMO). Otherwise, ABCD signaling is
reinserted on RPCMO as controlled by System Bus Per-Channel [SBCn; addr 0E0–0FF] and
RX Per-Channel [RPCn; addr 180–19F] controls.
0 = enable insertion of signaling onto RPCMO
1 = inhibit RPCMO signaling
RPCM_NEG
RSYN_NEG
Output Data on Falling Edge Clock—Selects RSBCKI rising or falling edge clock signal to
output RPCMO, RSIGO, RINDO, and SIGFRZ.
0 = RSB rising edge outputs
1 = RSB falling edge outputs
Output Sync on Falling Edge Clock—Selects RSBCKI rising or falling edge clock signal for
RFSYNC or RMSYNC outputs. Opposite RSBCKI edge is used if RFSYNC or RMSYNC is
programmed as an input.
0 = RFSYNC or RMSYNC rising edge output (falling edge input)
1 = RFSYNC or RMSYNC falling edge output (rising edge input)
BUS_FRZ
RSB_CTR
Enable Bused SIGFRZ Output—Enables SIGFRZ from multiple devices to share a common
receive system bus connection. When active, SIGFRZ three-states during bus group time slots
that are unused by the selected SBI mode [addr 0D0].
0 = SIGFRZ repeats for all bus groups
1 = three-state SIGFRZ during unused bus groups
Force RSLIP to Center—Writing a one to RSB_CTR forces RSLIP read buffer pointer to its
initial delay condition. If RFSYNC or RMSYNC is programmed as an output, RSB_CTR
consequently forces a change of system bus sync alignment. The processor must assert
RSB_CTR after configuration of the receive slip buffer. Centering RSLIP does not effect
RSLIP status reported in ISR.5 [addr 006].
0 = no effect
1 = force RSLIP to center
3-96
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
