3.0 Registers
CX28394/28395/28398
3.15 Data Link Registers
Quad/x16/Octal—T1/E1/J1 Framers
0BA—DLINK Test Configuration (DL_TEST1)
Data link test registers [addr 0BA-0BE] are for Conexant production test. Set to zero for normal operation.
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
—
—
—
—
DL_TEST1[3]
DL_TEST1[2]
DL_TEST1[1]
DL_TEST1[0]
DL_TEST1[3]
Clock Test—Zero for normal operation, where clocks controlled by DL1_CTL and DL2_CTL
[addr 0A6, 0B1]. When active high, clocks are always enabled.
DL_TEST1[2]
Shadow Select—Report shadow pointers instead of normal read/write pointers.
FIFO Select: 00 = RDL1; 01 = RDL2; 10 = TDL1; 11 = TDL2
DL_TEST1[1, 0]
0BB—DLINK Test Status (DL_TEST2)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
—
—
DL_TEST2[5]
DL_TEST2[4]
DL_TEST2[3]
DL_TEST2[2]
DL_TEST2[1]
DL_TEST2[0]
DL_TEST2[5:0]
Read or Shadow Read Pointer—Reports selected FIFO read pointer current address.
0BC—DLINK Test Status (DL_TEST3)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
—
—
DL_TEST3[5]
DL_TEST3[4]
DL_TEST3[3]
DL_TEST3[2]
DL_TEST3[1]
DL_TEST3[0]
DL_TEST3[5:0]
Write or Shadow Write Pointer—Specifies selected FIFO write pointer address.
0BD—DLINK Test Control #1 or Configuration #2 (DL_TEST4)
7
6
5
4
3
2
1
0
—
DL_TEST4[6]
DL_TEST4[5]
DL_TEST4[4]
DL_TEST4[3]
DL_TEST4[2]
DL_TEST4[1]
DL_TEST4[0]
DL_TEST4[6]
DL_TEST4[5]
DL_TEST4[4]
DL_TEST4[3]
DL_TEST4[2]
DL_TEST4[1]
DL_TEST4[0]
TFIFO1 Read Clear—Force transmit FIFO read pointer to empty.
TFIFO1 Write Clear—Force transmit FIFO write pointer to empty.
TFIFO1 Write—MPU data goes to specified write pointer address.
RFIFO1 Read Clear—Force receive FIFO read pointer to empty state (flush).
RFIFO1 Write Clear—Force receive FIFO write pointer to empty state (flush).
RFIFO1 Write—MPU data goes to specified write pointer address.
RFIFO1 Bypass—Pipe receive data.
3-92
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
