3.0 Registers
CX28394/28395/28398
3.15 Data Link Registers
Quad/x16/Octal—T1/E1/J1 Framers
0B6—TDL #2 FIFO Empty Control (TDL2_FEC)
7
6
5
4
3
2
1
0
—
—
FEC[5]
FEC[4]
FEC[3]
FEC[2]
FEC[1]
FEC[0]
FEC[5:0]
Near Empty Transmit FIFO Threshold—Selects a FIFO depth of near empty interrupt
[TNEAR; addr 00A] and near empty level status [TNEAR2; addr 0B9]. The TNEAR interrupt
is activated when the number of data bytes remaining to be transmitted from the FIFO falls
below the selected threshold. The TNEAR2 indicator is active as long as the number of
processor filled FIFO locations is below the selected threshold. Thus, TNEAR2 is active high
when the transmit FIFO is completely empty and remains active until the processor writes the
selected threshold number of bytes to TDL2 [addr 0B8]. Assuming the processor writes 64
bytes to completely fill an empty FIFO, TNEAR interrupt occurs after the transmitter has sent
the number of bytes required to bring the FIFO level back down below the selected threshold.
Hence, the processor is guaranteed to be able to consecutively write 64 – FEC[5:0] number of
bytes to the transmit FIFO in response to a TNEAR interrupt. The interrupt also signifies how
much time remains (in bytes) for the processor to write TDL2 before transmit FIFO is emptied.
Typically, FEC[5:0] is set to a small value (approximately 5–10 byte threshold) to minimize the
number of TNEAR interrupts and maximize the time between TNEAR interrupts.
FEC[5:0]
00 0000
00 0001
00 0010
|
Byte Threshold @ TNEAR
Disabled
Empty @ TNEAR
Disabled
63 empty
62 empty
|
1 byte threshold
2 byte threshold
|
11 1110
11 1111
62 byte threshold
63 byte threshold
2 empty
1 empty
0B7—TDL #2 End Of Message Control (TDL2_EOM)
7
6
5
4
3
2
1
0
EOM[7]
EOM[6]
EOM[5]
EOM[4]
EOM[3]
EOM[2]
EOM[1]
EOM[0]
TDL2_EOM
End of Transmit Message. Writing any data value to TDL2_EOM marks the last byte of data
written into the transmit FIFO as the end of an HDLC message (FCS or Non-FCS mode) or the
end of a transmit circular buffer. The processor must write TDL2_EOM after writing a
complete message or the last byte of a circular buffer into TDL2 [addr 0B8]. The written data
value is ignored and cannot be read back. Multiple HDLC messages are allowed to be queued
in the transmit FIFO simultaneously. In addition, the transition from one circular buffer to
another occurs only after the end of message byte of the current circular buffer has been sent.
3-90
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
