CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.16 System Bus Registers
RSBI[1:0]
Receive Slip Buffer Interface Mode—Selects configuration of RSLIP buffer. RSBI determines
the total buffer depth and initial delay conditions. While RSLIP is bypassed, RSB outputs and
RSBCKI is ignored. RFSYNC and RMSYNC are also ignored in bypass mode if they are
programmed as inputs.
RSBI
Mode
Total
Initial Delay
Conditions
Depth
00
Normal
2 Frame
1 Frame
When RFSYNC is output
0.5 to 1.5 Frames When RFSYNC is input
01
10
11
Short
2 Frame
32 bits
32 bits
0 bits
Reverts to normal upon slip
Recenters automatically upon slip
RSBCKI ignored
Elastic
Bypass
674 bits
0 bits
0D2—RSB Sync Bit Offset (RSYNC_BIT)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
—
—
—
—
—
OFFSET[2]
OFFSET[1]
OFFSET[0]
OFFSET[2:0]
RSB Sync Bit Offset—Selects which RSB bit number coincides with RFSYNC and RMSYNC
sync pulses. Sync pulses are programmed to align to one bit in relation to RPCMO, RSIGO,
RINDO, and SIGFRZ time slots. If the sync pulses are desired to coincide with location of T1
F-bit or time slot zero Bit 1, then OFFSET is programmed to equal zero. Sync bit offset is
added to time slot offset [RSYNC_TS; addr 0D3] to form a 10-bit OFFSET value. This value
applies to RFSYNC location, which is then added to frame offset [RSYNC_FRM; addr 0D8]
to form a 15-bit OFFSET value that applies to RMSYNC location. Both RFSYNC and
RMSYNC offsets are expressed as RSB.OFFSET, allowing the system to generate or accept
sync pulses at any bit location within the RSB multiframe.
OFFSET[2:0]
RSYNC Location
000
001
|
Bit 1 or F-bit
Bit 2
|
110
111
Bit 7
Bit 8
100054E
Conexant
3-97
CONEXANT [ CONEXANT SYSTEMS, INC ]
