CX25870/871
2.0 Internal Registers
Flicker-Free Video Encoder with Ultrascale Technology
2.4 Reading Registers
Table 2-5. Programming Detail For All Read/Write Registers (13 of 16)
Bit/Register
Names
Bit Location
Bit 6–38
Bit/Register Definition
Low resolution pixel doubling bit.
PIX_DOUBLE
0 = Encoder accepts each pixel input individually and processes it. (DEFAULT)
1 = Encoder replicates/copies each input pixel received. This bit is automatically set for
autoconfiguration modes #12, #13, and #41.
PKFIL_SEL[1:0]
PLL_32CLK
Bits [5:4]–D8
Bit 5–38
Text sharpening filter. Also referred to as the luma peaking filter selection (Refer to
Section 1.3.36 and Figure 1-27 for details).
00 = Bypass (DEFAULT)
01 = Filter 1 (1 dB gain)
10 = Filter 2 (2 dB gain)
11 = Filter 3 (3.5 dB gain)
Use this bit primarily to support the 1024 x 768 resolution and additional 800 x 600
overscan options. For more details, review the 3:2 Clocking Mode section.
0 = Use PLL 3x pixel clock output. (DEFAULT)
1 = Use PLL generated 2x pixel clock to run the encoder and output timing section. Use
PLL generated 3x pixel clock to run the flicker filter.
NOTE(S): The 3x pixel clock will be output from the CLKO pin during either state of this
bit.
PLL_DIV10
Bit 2–3A
Scales the CLKO frequency. (See Section 1.3.6 for details)
0 = PLL equation divided by 6. (DEFAULT)
1 = PLL equation divided by 10.
PLL_FRACT[15:0]
PLL_INPUT
Bits [7:0]–9E, -9C Fractional portion of PLL multiplier.
Bit 1–3A
0 = PLL uses the crystal between XTALIN and XTALOUT pins to generate the CLKO
programmed frequency. (DEFAULT)
1 = PLL uses CLKI/2 as the reference for the PLL.
PLL_INT[5:0]
Bits [5:0]–A0
Bit 4–30
Integer portion of PLL multiplier.
PLL_KEEP_ALIVE
0 = Normal operation. (DEFAULT)
1 = Keeps PLL enabled during the sleep mode. This bit is overwritten by DIS_PLL.
If the PLL is used to provide a system clock, this bit keeps it functioning if the rest of the
chip is slept through either the sleep pin or sleep bit. This bit has no affect if DIS_PLL is
set.
PROG_SC
Bit 0–D8
SECAM subcarrier control bit. PROG_SC only has an effect when FM bit is set.
0 = SECAM subcarrier is generated on lines 23–310 and 336–623. (DEFAULT)
1 = SECAM subcarrier is generated on the active lines defined by V_BLANKO[7:0] and
V_ACTIVEO[8:0].
RASTER_SEL[1:0]
Bits [1:0]–28
This bit is only effective when HDTV_EN = 1, and OUT_MODE[1:0] = 11
00 = Device does not generate trilevel sync automatically in HDTV output mode. Trilevel
sync periods dictated by active HSYNC* input signal (as HIGHSYNC) and active VSYNC*
input signal (as LOWSYNC). (DEFAULT)
01 = Trilevel sync generation for 480P format.
10 = Trilevel sync generation for 720P format.
11 = Trilevel sync generation for 1080I format.
REGFSCONV[5:0]
Reserved
Bits [5:0]–58
Various
Works in conjunction with FIL_4286INCR[7:0] to set gain on UV digital component.
Review the SECAM output section for the correct equations.
Reserved for future software compatibility; should be set to 0 for normal operation.
100381B
Conexant
2-21
CONEXANT [ CONEXANT SYSTEMS, INC ]
