2.0 Internal Registers
CX25870/871
2.4 Reading Registers
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (10 of 16)
Bit/Register
Names
Bit Location
Bit 7–A2
Bit/Register Definition
FM
This bit must be enabled for a valid SECAM video output.
0 = QAM color encoding (NTSC/PAL). (DEFAULT)
1 = FM color encoding (SECAM).
GY_SYNC_DIS
Bit 4–2E
This bit is only effective when OUT_MODE[1:0] = 11, HDTV_EN = 1, and RASTER_SEL is
nonzero.
0 = Enables trilevel sync on HDTV Green or Y output. (DEFAULT)
1 = Disables trilevel sync on HDTV Green or Y output.
H_ACTIVE[10:8]
H_ACTIVE[7:0]
Bits [6:4]–86 and Number of active input and output pixels.
bits [7:0]–78
H_BLANKI[9]
H_BLANKI[8]
H_BLANKI[7:0]
Bit 0–38, bit
3–8E, and
bits[7:0]–8C
Number of CLKI clock cycles between the digital HSYNC* leading edge and first active
pixel.
H_BLANKO[9:8]
H_BLANKO[7:0]
Bits [7:6]–9A and Number of CLKO clock cycles between leading edge of analog horizontal sync and active
bits [7:0]–80 video.
H_CLKI[10:8]
H_CLKI[7:0]
Bits [2:0]–8E and Number of CLKI clock cycles between consecutive leading edges of the digital HSYNC*
bits [7:0]–8A signal.
H_CLKO[11:8]
H_CLKO[7:0]
Bits [3:0]–86 and Number of CLKO clock cycles per analog line.
bits [7:0]–76
H_FRACT[7:0]
HALF_CLKO
Bits [7:0]–88
Bit 3–3A
Fractional number of input clocks per line. No effect if 00.
0 = Normal operation. (DEFAULT)
1 = CLKO (clock output) frequency divided by 2 while being transmitted.
HBURST_BEGIN[8] Bit2–38 and bits
This register contains the number of CLKO clock cycles between the analog horizontal
sync falling edge and the 50% point of the first colorburst cycle.
HBURST_BEGIN
[7:0]
[7:0]–7C
HBURST_END[8]
HBURST_END[7:0] [7:0]–7E
Bit 3–38 and bits This register contains the number of CLKO clock cycles minus 128 between the analog
horizontal sync falling edge and the 50% point of the last colorburst cycle. Make sure to
subtract 128 CLKO clock cycles from the calculated 50% point of the last colorburst
cycle value and load into this register.
HD_SYNC_EDGE
HDTV_EN
Bit 2–2E
Bit 7–28
This bit is only effective when OUT_MODE[1:0] = 11, HDTV_EN = 1 and RASTER_SEL is
nonzero.
0 = Trilevel sync edges transition time is equal to 4 input clocks. (DEFAULT)
1 = Trilevel sync edges transition time is equal to 2 input clocks.
Enable HDTV output mode, OUT_MODE[1:0] register bits must be set to 11 (VGA mode)
and EN_SCART must = 0.
0 = Enables VGA mode. DACs will output analog RGB with standard bilevel (-40 IRE)
analog syncs. (DEFAULT) See Section 1.3.45 for details.
1 = Enables HDTV output mode. DACs will output HDTV compatible RGB or component
video (Y/ PR/ PB) outputs. Trilevel syncs and vertical synchronizing/broad pulses will be
inserted automatically if RASTER_SEL[1:0] = nonzero.
NOTE(S): The EN_SCART bit must be 0 for HDTV Output Mode to be functional.
Analog horizontal sync width in number of CLKO clock cycles.
HSYNC_WIDTH
[7:0]
Bits [7:0]–7A
2-18
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
