2.0 Internal Registers
CX25870/871
2.4 Reading Registers
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (12 of 16)
Bit/Register
Names
Bit Location
Bit 7–D4
Bit/Register Definition
MODE2X
0 = Normal operation (DEFAULT).
1 = Divides selected input clock by two (allows for single edge rather than double-edge
clock input for pixel latching).
MSC[31:0]
Bits [7:0]–B4, B2, Subcarrier increment.
B0, AE
MSC_DB[31:0]
Bits [7:0]–48,
-46, -44, -42
Subcarrier increment for Db component of SECAM.
MSC_DB = int ((272/H_CLKO) * 232 + 0.5)
MY[7:0]
NI_OUT
Bits [7:0]–AC
Bit 0–A2
Multiplication factor for Luma component. Controls adjustment of contrast.
0 = Interlaced analog video output. (DEFAULT)
1 = Noninterlaced analog video output.
OFFSET_RGB
Bit 1–32
This bit is only effective when OUT_MODE[1:0] = 11, HDTV_EN = 1, and RASTER_SEL is
nonzero.
0 = Standard RGB digital input. Range is 0 – 255 decimal. (DEFAULT)
1 = HDTV OFFSET RGB digital input. Range is 16 – 235 decimal.
OUT_MODE[1:0]
Bits [3:2]–D6
00 = Video[0] = Composite (CVBS), Video[1] = Luminance (Y), Video[2] = Chrominance
(C), Video[3] = Luma_Delay (Y_DLY) (DEFAULT)
01 = Video[0-3] is CVBS_DLY/ Y/ C/ Y_DLY
10 = Video[0-3] is V/ Y/ U/ Y_DLY
11 = Video[0-3] is VGA (RGB/x), SCART, or HDTV output mode. See EN_SCART and
HDTV_EN bit descriptions for more programming detail.
OUT_MUXA[1:0]
OUT_MUXB[1:0]
OUT_MUXC[1:0]
OUT_MUXD[1:0]
PAL_MD
Bits [1:0]–CE
Bits [3:2]–CE
Bits [5:4]–CE
Bits [7:6]–CE
Bit 5–A2
00 = Output Video[0] on DACA (DEFAULT = Composite (CVBS))
01 = Output Video[1] on DACA
10 = Output Video[2] on DACA
11 = Output Video[3] on DACA
00 = Output Video[0] on DACB
01 = Output Video[1] on DACB (DEFAULT = Luminance (Y)
10 = Output Video[2] on DACB
11 = Output Video[3] on DACB
00 = Output Video[0] on DACC
01 = Output Video[1] on DACC
10 = Output Video[2] on DACC (DEFAULT = Chrominance)
11 = Output Video[3] on DACC
00 = Output Video[0] on DACD
01 = Output Video[1] on DACD
10 = Output Video[2] on DACD
11 = Output Video[3] on DACD (DEFAULT = Luma Delay (Y_DLY))
Video output switch bit after power-up.
0 = Disable phase alternation (NTSC and SECAM). (DEFAULT)
1 = Enable phase alternation (PAL).
NOTE(S): The PAL pin (#50) determines the power-up standard definition video output.
This bit overrides the PAL pin after power-up.
PHASE_OFF[7:0]
Bits [7:0]–B6
Subcarrier phase offset. Default value is 00. SCH Phase increased by 1.406 degrees per
bit increment.
2-20
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
