2.0 Internal Registers
CX25870/871
2.4 Reading Registers
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (14 of 16)
Bit/Register
Names
Bit Location
Bit 6–28
Bit/Register Definition
RGB2YPRPB
HDTV output switching bit. This bit is only effective when HDTV_EN = 1,
OUT_MODE[1:0] = 11, RASTER_SEL[1:0] = nonzero, and IN_MODE[3:0] = a RGB input
format.
0 = Digital RGB Input to HDTV RGB output. (DEFAULT)
1 = Digital RGB Input to HDTV YPRPB output.
RPR_SYNC_DIS
SC_PATTERN
Bit 5–28
Bit 1–D8
This bit is only effective when OUT_MODE[1:0] = 11, HDTV_EN = 1, and RASTER_SEL is
nonzero.
0 = Enables trilevel sync on HDTV Red or PR output. (DEFAULT)
1 = Disables trilevel sync on HDTV Red or PR output. This bit will have to be set manually
for EIA-770.3 compliance.
SECAM phase sequence. SC_PATTERN only has an effect when FM bit is set.
0 = 0° 0° 180° 0° 0° 180° SECAM subcarrier phase sequence. (DEFAULT)
1 = 0° 0° 0° 180° 180° 180° SECAM subcarrier phase sequence.
SERIALTEST[7:0]
SETUP
Bits [7:0]–28
Bit 1–A2
Use this register for testing the write and read ability of the serial master. A consecutive
write and read sequence will return the original value. The default value is 0x00.
0 = Setup off. The 7.5 IRE pedestal setup is disabled for active video lines (NTSC-J, PAL,
and SECAM).
1 = Setup on. The 7.5 IRE pedestal setup is enabled for active video lines (NTSC-M).
(DEFAULT)
SETUP_HOLD_ADJ Bit 4–32
0 = Graphic port inputs must have minimum setup = 3 ns, hold = 0 ns (DEFAULT). This
setting is compatible with Bt868/869.
1 = Graphics port inputs must have minimum setup = 1.25 ns, hold = 1.5 ns. This is a
new option for interfacing the CX25870/871 to other data master devices.
SLAVER
Bit 5–BA
Bit 7–30
Interface bit: Works in conjunction with EN_BLANKO, EN_DOT, and EN_OUT Controls
whether the interface will be timing Master or timing Slave.
0 = Configures encoder as the timing master. HSYNC* and VSYNC* will be transmitted
as outputs when this bit or a combination of this bit and SLAVE pin is 0. (DEFAULT)
1 = Configures encoder as the timing slave (pseudo-master or slave interface). HSYNC*
and VSYNC* will be received as inputs when this bit or a combination of this bit and
SLAVE pin is 1.
SLEEP_EN
0 = Normal operation. (DEFAULT)
1 = Enables sleep state.
Shuts down all internal clocks except the serial port interface clock. Disables all digital
I/O pins except: SLEEP, ALTADDR, CLKI, CLKO, and XTALOUT. Disables the PLL. Turns
off all DACs and VREF. SLEEP and RESET* pins are never disabled.
SRESET
Bit 7–BA
0 = Normal Operation. (DEFAULT)
1 = Setting this bit performs a software reset. All registers are reset to their default state.
This bit is automatically cleared.
SYNC_AMP[7:0]
TIMING_RST
Bits [7:0]–A4
Bit 7–6C
Multiplication factor for controlling the analog sync amplitude.
SYNC_AMP + 1 LSb (least significant bit) = +1.25 mV increase in the analog sync
amplitude.
0 = Normal Operation. (DEFAULT)
1 = Enable timing reset. Resets timing and pixel counters to 1 This bit is automatically
cleared. The designer should wait a minimum of 1 ms, after the last register write before
enabling TIMING_RST.
V_ACTIVEI[9:8]
V_ACTIVEI[7:0]
Bits [3:2]–96 and Number of active input lines.
Bits [7:0]–94
2-22
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
