CX25870/871
2.0 Internal Registers
Flicker-Free Video Encoder with Ultrascale Technology
2.4 Reading Registers
Table 2-5. Programming Detail For All Read/Write Registers (9 of 16)
Bit/Register
Bit Location
Names
Bit/Register Definition
F_SELC[2:0]
Bits [5:3]–C8
Chroma Standard Flicker Filter:
000 = 5 Line (DEFAULT)
001 = 2 Line
010 = 3 Line
011 = 4 Line
100 = Alternate 5 Line
101 = Alternate 5 Line
110 = Alternate 5 Line
111 = Alternate 5 Line
F_SELY[2:0]
Bits [2:0]–C8
Luma Standard Flicker Filter:
000 = 5 Line (DEFAULT)
001 = 2 Line
010 = 3 Line
011 = 4 Line
100 = Alternate 5 Line
101 = Alternate 5 Line
110 = Alternate 5 Line
111 = Alternate 5 Line
FFCBAR
FFRTN
Bit 5–6C
Bit 7–36
0 = Normal operation. (DEFAULT)
1 = Enable flicker filtered color bars.
Alternate flicker filter detect and select. This bit is effective only when ADPT_FF = 1.
0 = Once the adaptive algorithm selects the alternate filter, use that filter’s coefficients for
the rest of the samples for that line. For example, the sequence could be
STD/STD/ALT/ALT/ALT; (DEFAULT)
1 = Once the adaptive algorithm selects the alternate filter, use the filter’s coefficients for
that sample only. For example, the sequence with FFRTN=1 could be
STD/STD/ALT/STD/STD.
FIELD_ID
Bit 3–D8
0 = Suppress the SECAM field synchronization signal. (DEFAULT)
1 = Enable the SECAM field synchronization signal (bottle-neck pulses).
FIELDI
Bit 5–C6
0 = Logical 1 from the FIELD pin indicates an even field. (DEFAULT)
1 = Logical 1 from the FIELD pin indicates an odd field.
FILFSCONV[5:0]
FIL4286INCR[7:0]
FLD_MODE[1:0]
Bits [5:0]–58
Bits [7:0]–56
Bits [1:0]–6C
Adjust SECAM high frequency preemphasis filter according to the clock frequency.
Review the SECAM Output section for the correct equations.
Adds a phase offset to the UV digital components.
Review the SECAM Output section for the correct equations.
CX25870/871 uses this bit to interpret HSYNC* and VSYNC* edges and field detection in
slave mode.
00 = A leading edge of VSYNC* that occurs within ±1/4 of HCLKI from the leading edge
of HSYNC* indicates the beginning of odd field. A leading edge of VSYNC* that occurs
within ±1/4 of HCLKI from the center of the line indicates the beginning of even field.
01 = A leading edge of VSYNC* occurs during HSYNC* active indicates the beginning of
odd field. A leading edge of VSYNC* occurs during HSYNC* inactive indicates the
beginning of even field.
10 = A leading edge of VSYNC* coincides with the leading edge of HSYNC* indicates the
beginning of odd field. A leading edge of VSYNC* does not coincide with the leading
edge of HSYNC* indicated the beginning of even field. (DEFAULT)
11 = Reserved.
100381B
Conexant
2-17
CONEXANT [ CONEXANT SYSTEMS, INC ]
