3
3.0 PC Board Considerations
For optimum performance of the CX25870/871, proper CMOS layout techniques
should be studied before PC board layout is begun.
The layout should be optimized for lowest noise on the power and ground
planes by providing good decoupling. The trace length between groups of VAA
(or VDD) and GND (or VSS) pins should be as short as possible to minimize
inductive ringing.
A well-designed power distribution network is critical to eliminating digital
switching noise. The ground plane must provide a low-impedance return path for
the digital circuits. A PC board with a minimum of four layers is recommended,
with layers 1 (top) and 4 (bottom) for signals, and layers 2 and 3 for ground and
power, respectively.
3.1 Component Placement
Components should be placed as close as possible to the associated pin in order
for traces to be connected point to point. The optimum layout places the
CX25870/871 as close as possible to the power supply connector and the video
output connector, as illustrated in Figure 3-1.
Some other PC board layout tips to follow are:
•
Include a silk screen layer of labels in your layout artwork showing each
component and its reference designation. Label numbered test nodes and
the correct polarity of diodes and electrolytic capacitors.
Leave adequate space around components so ESD transients only have
minimally adverse effects on ICs.
•
•
Make sure signals that need access for troubleshooting or analysis are easy
to find and probe.
100381B
Conexant
3-1
CONEXANT [ CONEXANT SYSTEMS, INC ]
