CX25870/871
2.0 Internal Registers
Flicker-Free Video Encoder with Ultrascale Technology
2.4 Reading Registers
Table 2-5. Programming Detail For All Read/Write Registers (15 of 16)
Bit/Register
Names
Bit Location
Bit/Register Definition
V_ACTIVEO[8]
V_ACTIVEO[7:0]
Bit 7–86 and Bits Number of active output lines/field.
[7:0]–84
V_BLANKI[7:0]
V_BLANKO[7:0]
Bits [7:0]–92
Bits [7:0]–82
Number of input lines between VSYNC* leading edge and first active line.
Line number of first active output line (number of blank lines + 1).
V_LINESI[10]
V_LINESI[9:8]
V_LINESI[7:0]
Bit 1–38,
[1:0]–96, Bits
[7:0]–90
Bits Number of vertical input lines. This register value must match the graphic controller’s
VTOTAL register for a new overscan ratio.
V_SCALE[13:8]
V_SCALE[7:0]
Bits [5:0]–9A and Vertical scaling coefficient.
Bits {7:0]–98
VSR = V_ACTIVEI / (ALO * (1 – VOC))
V_SCALE[13:0] = (int) ((VSR – 1) * 212
)
VBLANKDLY
VSYNC_DUR
Bit 4–8E
0 = Normal operation. (DEFAULT)
1 = The effective vertical blanking value in the second field is V_BLANKI+1. Commonly
used in CCIR601 input. No effect if 0.
Bit 3–A2
0 = Generates 2.5 line VSYNC analog output (found in equalization and serration pulse
region). Common for most PAL and SECAM formats.
1 = Generates 3 line VSYNC analog output (found in equalization and serration pulse
region). Common for all NTSC, PAL-N, PAL-M, and PAL-60 formats. (DEFAULT)
VSYNCI
Bit 4–C6
0 = CX25870/871 transmits or receives active digital low VSYNC*. (DEFAULT)
1 = CX25870/871 transmits or receives active digital high VSYNC*.
VSYNWIDTH[2:0]
Bits [2:0]–74
Controls the width of the VSYNC* output pulse. Denotes the number of lines the
VSYNC* digital signal remains low on field transitions. Value will be hexadecimal and its
units are in terms of lines. A value of 0 is a disallowed condition. The acceptable range is
1 line to (23 –1) lines. The default value is 1. Never set to 0. This register is only effective
in master interface.
WSSDAT[20:1]
Bits [7:0]–64,
- 62, and
Wide screen signaling (WSS) data bits. Review WSS section for more details.
bits [3:0]–60
WSSINC[19:0]
XDSSEL[3:0]
Bits [3:0]–6A and WSS DTO increment bits. Review WSS section for more details.
bits [7:0]–68, - 66
Bits [7:4]–5E
Line position of Extended Data Services (XDS) Content.
Controls which line contains Extended Data Services data. Each line enable is
independent of the other.
0001 = Extended Data Services on line 282 (525-line) and line 333 (625-line).
0010 = Extended Data Services on line 283 (525-line) and line 334 (625-line).
0100 = Extended Data Services on line 284 (525-line) and line 335 (625-line).
(DEFAULT)
1000 = Extended Data Services on line 285 (525-line) and line 336 (625-line).
XTL_BFO_DIS
Bit 5–30
Bit 6–30
On power-up, a 50% duty cycle buffered output will be transmitted at the frequency
found between the XTALIN and XTALOUT ports from the XTL_BFO pin #3.
0 = Enable buffer crystal clock output. [DEFAULT]
1 = Disable buffer crystal clock output.
XTAL_PAD_DIS
0 = Normal operation. (DEFAULT)
1 = Disable XTALIN and XTALOUT crystal pin. Encoder must receive main clock through
CLKI pin.
100381B
Conexant
2-23
CONEXANT [ CONEXANT SYSTEMS, INC ]
