2.0 Internal Registers
CX25870/871
2.4 Reading Registers
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (8 of 16)
Bit/Register
Bit Location
Names
Bit/Register Definition
0 = Normal closed-caption encoding. (DEFAULT)
ECCGATE
Bit 3–C4
1 = Enables closed-caption encoding constraints. After encoding, future encoding is
disabled until a complete pair of new data bytes is received. This prevents encoding of
redundant or incomplete data.
ECLIP
Bit 6–A2
Bit 5–D4
0 = Normal operation. (DEFAULT)
1 = Enable clipping; DAC values less than 31 hex are made 31 by the encoder.
EN_ASYNC
0 = Normal operation. (DEFAULT)
1 = Enable asynchronous flicker filer and encoder block timing operation. Use CLKI for
flicker filter and input blocks and PLL for encoder block. Allows for additional clock
ratios between flicker filter and encoder blocks to provide more overscan solutions
similar to the 3:2 clocking mode.
EN_BLANKO
EN_DOT
Bit 7–C6
Bit 6–C6
Interface bit: Works in conjunction with EN_DOT, EN_OUT, and SLAVER. Controls
direction of BLANK* signal.
0 = Enables BLANK* as an input.
1 = Enables BLANK* pin as an output, or no BLANK* signal is utilized in the system
interface. (DEFAULT)
Interface bit: Works in conjunction with EN_BLANKO, EN_OUT, and SLAVER. Controls
blanking method.
0 = Encoder uses its internal counters to determine the active-versus-blanked regions of
input data. (DEFAULT)
1 = Encoder uses the BLANK* signal being received to determine where active video
starts (rising edge by default) and where blanking region starts (falling edge by default).
EN_OUT
Bit 0–C4
Interface bit: Works in conjunction with EN_BLANKO, EN_DOT, and SLAVER. Turns
timing outputs on or off.
0 = Three-state (CLKO, HSYNC*, VSYNC*, BLANK* and FIELD) timing outputs.
(DEFAULT)
1 = Allows CLKO and other outputs to be enabled (depending upon EN_BLANKO register
bit and the OR combination of the SLAVE pin and the SLAVER bit).
EN_REG_RD
EN_SCART
Bit 6–6C
Bit 3–6C
0 = Use ESTATUS[1:0] register to select read back status registers. Enable Bt869-like
Legacy read-back method. (DEFAULT)
1 = Enable Standard serial register read back of all registers.
Enables SCART video output for Europe. OUT_MODE[1:0] field must be set to 11 (VGA
Mode) and HDTV_EN bit must be set to 0.
0 = Enables VGA mode. DACs will output analog RGB with standard bilevel (-40 IRE)
analog syncs (DEFAULT).
1 = Enables SCART output mode. DAC will transmit SCART compatible RGB outputs and
a composite video output which includes an analog sync.
EN_XCLK
ESTATUS[1:0]
EWSSF1
Bit 7–A0
0 = Encoder generates pixel clock. (DEFAULT)
1 = Use CLKI pin as pixel clock source. This bit must be set for slave interface.
Bits [7:6]–C4
Bit 6–60
Bt868/869 Legacy serial read back status bit selection. Used in conjunction with
EN_REG_RD, CHECK_STAT, and AUTO_CHK. Review Table 1-30.
0 = Disable field 1 WSS data. (DEFAULT)
1 = Enable field 1 WSS data.
EWSSF2
Bit 7–60
0 = Disable field 2 WSS data. (DEFAULT)
1 = Enable field 2 WSS data (525 line only).
2-16
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
