2.0 Internal Registers
CX25870/871
2.4 Reading Registers
Flicker-Free Video Encoder with Ultrascale Technology
Table 2-5. Programming Detail For All Read/Write Registers (6 of 16)
Bit/Register
Bit Location
Names
Bit/Register Definition
DACDISC
DACDISD
DACOFF
DATDLY
Bit 2–BA
Bit 3–BA
Bit 4–BA
Bit 7–74
No more than 1 DAC should be disabled at any time.
0 = Normal operation. (DEFAULT)
1 = Disables DACC output. Current is set to 0 mA; output will go to 0 V.
No more than 1 DAC should be disabled at any time.
0 = Normal Operation. (DEFAULT)
1 = Disables DACD output. Current is set to 0 mA; output will go to 0 V.
0 = Normal operation. (DEFAULT)
1 = Disables DAC output current and internal voltage reference for all DACs. This will
limit power consumption to just the internal digital circuitry.
0 = No delay in falling edge pixel data. (DEFAULT)
1 = Delays the falling edge pixel data by 1 full clock period. This bit is used to correct a
multiplexed input data sequence that delivers a pixel on a falling edge and the following
rising edge (rather than a rising edge and the following falling edge, as expected).
DATDLY_RE
DATSWP
Bit 2–32
Bit 6–74
0 = No delay in rising edge pixel data. (DEFAULT)
1 = Delays the rising edge pixel data by 1 full clock period. This bit is used together with
DATSWP to correct a multiplexed input data sequence that delivers a pixel on a falling
edge and the following rising edge with the falling edge and rising edge data swapped.
0 = VGA Encoder expects an order of rising edge data/falling edge data coming from the
graphics controller (DEFAULT).
1 = Swaps the falling edge pixel data with the rising edge pixel data at the input of the
pixel port.
DB_LIMITN[10:8}
DB_LIMITN[7:0]
Bits [5:3]–54 and Lower bound limit for DB frequency deviation in SECAM. Review SECAM Output Section.
bits [7:0]–52
DB_LIMITP[10:8}
DB_LIMITP[7:0]
Bits [2:0]–54 and Upper bound limit for DB frequency deviation in SECAM. Review SECAM Output Section.
bits [7:0]–50
DCHROMA
Bit 1–C4
0 = Normal operation. (DEFAULT)
1 = Disable the chrominance portion of video output. Composite and S-Video outputs
appear as gray scale.
DIS_CLKI
Bit 3–30
0 = Normal operation. (DEFAULT)
1 = Disable CLKI input.
Disabling the CLKI input is separate from the sleep bit and SLEEP pin. This forces the
CX25870/871 to use an external clock as the clock source for the CX25870/871 or as the
PLL input.
DIS_CLKO
Bit 1–30
0 = Enable CLKO output. (DEFAULT)
1 = Three-state CLKO output.
This will disable the CLKO output when not needed, i.e., an external clock is used (Slave
Interface). Disabling CLKO is also effective in reducing the current draw in SLEEP mode.
DIS_FFILT
Bit 6–C8
Bit 6–CC
Bit 6–CA
Bit 7–CC
0 = Enables Standard Flicker Filter. (DEFAULT)
1 = Disables Standard Flicker Filter.
DIS_GMSHC
DIS_GMSHY
DIS_GMUSHC
0 = Enables Chroma Pseudo Gamma Removal.
1 = Disables Chroma Pseudo Gamma Removal. (DEFAULT)
0 = Enables Luma Pseudo Gamma Removal.
1 = Disables Luma Pseudo Gamma Removal. (DEFAULT)
0 = Enables Chroma Anti-Pseudo Gamma Removal.
1 = Disables Chroma Anti-Pseudo Gamma Removal. (DEFAULT)
2-14
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
