2.0 Circuit Description
2.4 Receiver
Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
Figure 2-14. Interrupt Driven Receive Data Link Processing
Interrupt Service Routine
Interrupt Occurred
Read Interrupt Status
Complete MSG
or Near Full
Interrupt
No
Yes
Read Data Link Status
Process Other Interrupt
Return
Read Message Byte from FIFO
and Discard
If
No
Message Status
(Purge FIFO)
on FIFO
Yes
Read Message Status from FIFO
Read X Message Bytes from FIFO
If
Yes
Message Status
is Good or
Continue
Return
No
Error Receiving Message
Return
NOTE(S): Message status contains number of message bytes (X) in FIFO where (X) equals 0 during idle channel or errored
message.
2-30
Conexant
N8370DSE