Bt8370/8375/8376
2.0 Circuit Description
2.5 Receive System Bus
Fully Integrated T1/E1 Framer and Line Interface
The RSB supports five system bus rates (MHz): 1.536, 1.544, 2.048, 4.096,
and 8.192. The T1 rate without a framing bit is 1.536 MHz, consisting of 24 time
slots. The T1 rate with a framing bit 1.544 MHz. The E1 rate is 2.048 MHz,
consisting of 32 time slots. Twice the E1 rate is 4.096 MHz, consisting of 64 time
slots. Four times the E1 rate is 8.192 MHz, consisting of 128 time slots. The
4.096 and 8.192 MHz bus modes contain multiple bus members (A, B, C, D)
which allow multiple T1/E1 signals to share the same system bus. This is done by
interleaving the time slots to a maximum of four Bt8370s without external
circuitry (see Figures 2-15 and 2-17). The system bus rate is independent of the
line rate and must be selected using the System Bus Interface Configuration
register [SBI_CR; addr 0D0].
Figure 2-16. RSB 4.096 MHz Bus Mode Time Slot Interleaving
RSBCKI
RPCMO
TS31A
TS31B
TS0A
TS0B
RSIGO
SIG31A
SIG31B
SIG0A
SIG0B
RFSYNC
NOTE(S): A and B time slot data comes from different Bt8370s. Output data on rising edge clock, RCPM_NEG = 0 [addr 0D1].
Output sync on rising edge clock, RSYN_NEG = 0 [addr 0D1]. RSBCKI operates at 1 times the data rate. RSB.OFFSET
equals 0.
Figure 2-17. RSB 8.192 MHz Bus Mode Time Slot Interleaving
RSBCKI
RPCMO
RSIGO
TS31A
TS31B
TS31C
TS31D
TS0A
TS0B
TS0C
TS0D
SIG31A
SIG31B
SIG31C
SIG31D
SIG0A
SIG0B
SIG0C
SIG0D
RFSYNC
NOTE(S): A, B, C, and D data comes from different Bt8370s. Output data on rising edge clock, RCPM_NEG = 0 [addr 0D1].
Output sync on rising edge clock, RSYN_NEG = 0 [addr 0D1]. RSBCKI operates at 1 times the data rate. RSB.OFFSET
equals 0.
N8370DSE
Conexant
2-33