2.0 Circuit Description
2.4 Receiver
Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
The time slot and bit selection are performed through the DL1 Time Slot
Enable register [DL1_TS; addr 0A4] and the DL1 Bit Enable register [DL1_BIT;
addr 0A5]. The DL1 Time Slot Enable register selects the frames and time slot to
extract the data link. The frame select tells the receiver to extract the time slot in
all frames, odd frames, even frames. The time slot enable is a value between 0 and
31 that selects which time slot to extract. The DL1 Bit Enable register selects
which bits are extracted in the selected time slot. Refer to Table 2-4 for the
common frame, time slot, time slot bits, and modes used.
The Receive Data Link FIFO #1 [RDL1; addr 0A8] is 64 bytes long. The
Receive FIFO is formatted differently than the transmit FIFO. The Receive FIFO
contains not only received messages, but also a status byte preceding each
message that specifies the size of the received message and the status of that
message. The message status reports if the message was aborted, received with a
correct/incorrect FCS, or continued. A continued message means the byte count
represents a partial message. Once all message bytes are read, the FIFO contains
another status byte. Message bytes can be differentiated from status bytes in the
FIFO by reading the RSTAT1 bit in the RDL #1 Status register [RDL1_STAT;
addr 0A9]. RSTAT1 reports whether the next byte read from the FIFO is a status
byte or some number of message bytes.
The receive data link controller has a versatile microprocessor interface that
can be tuned to the system’s CPU bandwidth. For systems with 1 CPU dedicated
to 1 Bt8370, the data link status can be polled. For systems where a single CPU
controls multiple Bt8370s, the data link can be interrupt-driven. See Figures 2-13
and 2-14 for a high-level description of polling and interrupt driven Receive Data
Link Controller software.
2-28
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
