2.0 Circuit Description
2.5 Receive System Bus
Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
The RSB maps line rate time slots to system bus time slots. The 24- (DS1) or
32- (CEPT) line rate time slots can be mapped to 24, 32, 64, or 128 system bus
time slots as listed in Table 2-5. The system bus rate must be greater than or equal
to the line rate, except for 1.536 MHz bus mode.
Table 2-5. RSB Interface Time Slot Mapping
Destination
Time Slots
Line Rate (MHz)
Source Channels
System Bus Rate (MHz)
1.544
24
24
24
24
24
32
32
32
1.536
1.544
2.048
4.096
8.192
2.048
4.096
8.192
24
24
32
64
128
32
2.048
64
128
The RSB, illustrated in Figure 2-18, consists of a timebase, slip buffer,
signaling buffer, and signaling stack.
Figure 2-18. RSB Diagram
RSIG
Buffer
RSIG
STACK
+
RSIG
Local
RSIGO
+
RPCMO
SIGFRZ
RSLIP
Buffer
RNRZ
AIS
RINDO
RFSYNC
RMSYNC
From
Receiver
RSB
Timebase
RPHASE
Remote
Channel
Loopback
Local
Channel
Loopback
RSBCKI
TSBCKI
CLADI
CLADO
2-34
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
