Bt8370/8375/8376
2.0 Circuit Description
2.4 Receiver
Fully Integrated T1/E1 Framer and Line Interface
2.4.10.1 Data Link
Controllers
The Bt8370 and Bt8375 provide two internal data link controllers, and the Bt8376
provides a single controller (DL1). DL1 and DL2 control two serial data channels
operating at multiples of 4 kbps—up to the full 64 kbps time slot rate—by
selecting a combination of bits from odd, even, or all frames. Both DL1 and DL2
support the following: ESF Facilities Data Link (FDL), SLC-96 Data Link,
Sa Data Link, Common Channel Signaling (CCS), Signaling System #7 (SS7),
ISDN LAPD channels, Digital Multiplexed Interface (DMI) Signaling in TS24,
ETSI V.5.1 and V.5.2 control channels. DL1 and DL2 each contain a 64-byte
receive buffer that functions as either programmable length circular buffers or
full-length data FIFOs.
Both data link controllers are configured identically, except for their offset in
the register map. The DL1 address range is 0A4 to 0AE, and the DL2 address
range is 0AF to 0B9. From this point on, DL1 is used to describe the operation of
both data link controllers.
DL1 is enabled using the DL1 Control register [DL1_CTL; addr 0A6]. DL1
does not function until it is enabled. DL1_CTL also controls the format of the
data. The following data formats [DL1[1:0]; addr 0A6] are supported on the data
link: Frame Check Sequence (FCS), non-FCS, Pack8, or Pack6. FCS and
non-FCS are HDLC formatted messages. Pack8 and Pack6 are unformatted
messages with 8 bits per FIFO access, or 6 bits per FIFO access, respectively
(see Table 2-4).
Table 2-4. Commonly Used Data Link Settings
Data Link
ESF FDL
Frame
Time Slot
Time Slot Bits
Mode
Odd
All
0 (F-bits)
Don’t Care
00000010
Don’t Care
11111111
00001000
FCS
FCS
T1DM R Bit
SLC-96
24
Even
All
0 (F-bits)
Pack6
FCS
ISDN LAPD
Sa4
N
1
Odd
FCS
NOTE(S): N represents any T1/E1 time slot.
N8370DSE
Conexant
2-27
CONEXANT [ CONEXANT SYSTEMS, INC ]
