Bt8370/8375/8376
3.0 Registers
Fully Integrated T1/E1 Framer and Line Interface
3.1 Address Map
Table 3-1. Address Map (7 of 8)
Default Register Setting
Address
(Hex)
Acronym
R/W
Description
Bt8370
Bt8375
Bt8376
0D0
SBI_CR
RSB_CR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
System Bus Interface
Configuration
00
00
00
0D1
0D2
0D3
0D4
0D5
0D6
0D7
0D8
Receive System Bus
Configuration
00
—
—
00
—
—
—
—
00
—
—
00
—
—
—
—
00
—
—
00
—
—
—
—
RSYNC_BIT
RSYNC_TS
TSB_CR
Receive System Bus Sync Bit
Offset
Receive System Bus Sync
Time Slot Offset
Transmit System Bus
Configuration
TSYNC_BIT
TSYNC_TS
RSIG_CR
Transmit System Bus Sync Bit
Offset
Transmit System Bus Sync
Time Slot Offset
Receive Signaling
Configuration
RSYNC_FRM
Signaling Reinsertion Frame
Offset
0D9
0DA
SSTAT
STACK
RPHASE
TPHASE
PERR
R
R
Slip Buffer Status
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Signaling Stack
RSLIP Phase Status
TSLIP Phase Status
RAM Parity Status
0DB
R
0DC
R
0DD
R
0E0–0FF
SBCn:
n = 0 to 31
R/W
System Bus Per-Channel
Control
N8370DSE
Conexant
3-7
CONEXANT [ CONEXANT SYSTEMS, INC ]
