3.0 Registers
Bt8370/8375/8376
3.1 Address Map
Fully Integrated T1/E1 Framer and Line Interface
Table 3-1. Address Map (4 of 8)
Default Register Setting
Address
Acronym
(Hex)
R/W
Description
Bt8370
Bt8375
Bt8376
050
051
FERR
FERR
R
R
Framing Bit Error Counter LSB
—
—
—
—
—
—
Framing Bit Error Counter
MSB
052
053
054
CERR
CERR
LCV
R
R
R
CRC Error Counter LSB
CRC Error Counter MSB
—
—
—
—
—
—
—
—
—
Line Code Violation Counter
LSB
055
056
057
LCV
FEBE
FEBE
R
R
R
Line Code Violation Counter
MSB
—
—
—
—
—
—
—
—
—
Far End Block Error Counter
LSB
Far End Block Error Counter
MSB
058
059
BERR
BERR
RSA4
RSA5
RSA6
RSA7
RSA8
SHAPE
R
R
PRBS Bit Error Counter LSB
PRBS Bit Error Counter MSB
Receive Sa4 Byte Buffer
Receive Sa5 Byte Buffer
Receive Sa6 Byte Buffer
Receive Sa7 Byte Buffer
Receive Sa8 Byte Buffer
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
05B
R
05C
R
05D
R
05E
R
05F
R
060–067
R/W
Transmit Pulse Shape
Configuration
15, 14,
14, 14, 6,
4, 2, 1
15, 14,
14, 14, 6,
4, 2, 1
15, 14,
14, 14, 6,
4, 2, 1
068
TLIU_CR
R/W
Transmit LIU Configuration
01
01
01
3-4
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
