Bt8370/8375/8376
3.0 Registers
Fully Integrated T1/E1 Framer and Line Interface
3.2 Global Control and Status Registers
3.2 Global Control and Status Registers
Unused bits indicated by a dash (—) are reserved and should be written to 0. Writing to reserved bits has no
effect.
000—Device Identification (DID)
Read only value.
7
6
5
4
3
2
1
0
DID[7]
DID[6]
DID[5]
DID[4]
DID[3]
DID[2]
DID[1]
DID[0]
DID[7:4]
Device ID—A value of 0x0 indicates Bt8370.
A value of 0x5 indicates the Bt8375.
A value of 0x6 indicates the Bt8376.
DID[3:0]
Device Revision—A value of 0x8 indicates the current revision. Prior revisions are obsolete.
001—Primary Control Register (CR0)
7
6
5
4
3
2
1
0
RESET
—
—
RFRAME[3]
RFRAME[2]
RFRAME[1]
RFRAME[0]
T1/E1N
RESET
Device Reset—Active-high indicates a device reset is in progress. The device reset is initiated
by a power-on reset, a software reset, or a hardware reset (RST* pin is active low). RESET can
be monitored to determine when the reset process is complete.
To initiate a software reset, the processor must first write RESET to 0, then delay at least
6 µs, then write RESET to 1. Once initiated, the reset process continues for 15 µs maximum,
and causes the Bt8370/8375/8376 to initialize certain control registers to their default settings,
as shown in Table 3-1, Address Map. The processor must not write to these registers until
RESET returns low, although other non-default registers can be processor-initialized while
RESET is active.
To avoid non-compliant line rate or pulse shape transmissions during the reset process, the
system can three-state the transmit line driver by holding the XOE pin inactive (low).
After the reset process, the following is true:
1. System bus outputs RSIGO, RPCMO, and SIGFRZO are three-stated.
2. Interrupt INTR* output is disabled.
3. Programmable I/O pins are configured as inputs: RFSYNC, RMSYNC,
TFSYNC, TMSYNC, TNEGI/TDLCLKO, and ONESEC.
4. CONEXANT production test modes are disabled.
N8370DSE
Conexant
3-9
CONEXANT [ CONEXANT SYSTEMS, INC ]
