3.0 Registers
Bt8370/8375/8376
3.1 Address Map
Fully Integrated T1/E1 Framer and Line Interface
Table 3-1. Address Map (6 of 8)
Default Register Setting
Address
Acronym
(Hex)
R/W
Description
Bt8370
Bt8375
Bt8376
0A4
0A5
0A6
0A7
0A8
0A9
0AA
0AB
0AC
DL1_TS
DL1_BIT
DL1_CTL
RDL1_FFC
RDL1
R/W
R/W
R/W
R/W
R
DL1 Time Slot Enable
DL1 Bit Enable
00
00
00
00
—
—
00
00
—
00
00
00
00
—
—
00
00
—
00
00
00
00
—
—
00
00
—
DL1 Control
RDL #1 FIFO Fill Control
Receive Data Link FIFO #1
RDL #1 Status
RDL1_STAT
PRM
R
R/W
R/W
W
Performance Report Message
TDL #1 FIFO Empty Control
TDL1_FEC
TDL1_EOM
TDL #1 End Of Message
Control
0AD
0AE
0AF
0B0
0B1
0B2
0B3
0B4
0B6
0B7
TDL1
R/W
R
Transmit Data Link FIFO #1
TDL #1 Status
—
—
00
00
00
00
—
—
00
—
—
—
00
00
00
00
—
—
00
—
—
—
TDL1_STAT
DL2_TS
R/W
R/W
R/W
R/W
R
DL2 Time Slot Enable
DL2 Bit Enable
N/A
N/A
N/A
N/A
—
DL2_BIT
DL2_CTL
RDL2_FFC
RDL2
DL2 Control
RDL #2 FIFO Fill Control
Receive Data Link FIFO #2
RDL #2 Status
RDL2_STAT
TDL2_FEC
TDL2_EOM
R
—
R/W
W
TDL #2 FIFO Empty Control
N/A
—
TDL #2 End Of Message
Control
0B8
0B9
0BA
0BB
0BC
0BD
TDL2
R/W
R
Transmit Data Link FIFO #2
TDL #2 Status
—
—
00
00
00
00
—
—
00
00
00
00
—
—
00
00
00
00
TDL2_STAT
DL_TEST1
DL_TEST2
DL_TEST3
DL_TEST4
R/W
R/W
R/W
R/W
DLINK Test Configuration
DLINK Test Status
DLINK Test Status
DLINK Test Control #1 or
Configuration #2
0BE
DL_TEST5
R/W
DLINK Test Control #2 or
Configuration #2
00
00
00
3-6
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
