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BT8375EPF 参数 Datasheet PDF下载

BT8375EPF图片预览
型号: BT8375EPF
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片收发器T1 / E1和综合业务数字网( ISDN )基本速率接口 [single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces]
分类和应用: 电信集成电路综合业务数字网
文件页数/大小: 323 页 / 1950 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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Bt8370/8375/8376  
3.0 Registers  
Fully Integrated T1/E1 Framer and Line Interface  
3.2 Global Control and Status Registers  
002Jitter Attenuator Configuration (JAT_CR)  
The processor writes JAT_CR register at power-up, activating the JAUTO and JCENTER bits to initialize the  
jitter attenuator elastic store. The processor can maximize jitter tolerance by repeating JCENTER after  
recovering from an error [CKERR; addr 006] on the JAT input clock reference. JAT elastic store automatically  
recenters upon detection of an elastic store limit error [JERR; addr 006].  
7
6
5
4
3
2
1
0
JEN  
JFREE  
JDIR  
JAUTO  
JCENTER  
JSIZE[2]  
JSIZE[1]  
JSIZE[0]  
JEN  
Jitter Attenuator EnableJCLK and CLADO are locked to the timing reference selected. The  
reference frequency can operate at T1 or E1 line rates, or at any rate supported by the clock  
rate adapter. See RSCALE[2:0] [addr 092] for selecting the timing reference frequency.  
CEN JEN JFREE JDIR  
CLADO/JCLK Reference  
0
0
0
0
0
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
0
X
0
REFCKIFree running 10 MHz clock  
REFCKIFree running 10 MHz clock with transmit JAT  
REFCKIFree running 10 MHz clock with receive JAT  
TXCLKTCKI or ACKI per [AISCLK; addr 068]  
RXCLKRPLL or RCKI per [RDIGI; addr 020]  
CLADISystem clock, bypass JAT elastic store  
CLADISystem clock with transmit JAT  
1
0
1
X
0
1
CLADISystem clock with receive JAT  
NOTE: JCLK always operates at T1 or E1 line rate selected by [T1/E1N; addr 001].  
JFREE  
Free-Running JCLK and CLADODisables both CLADI and JAT phase detectors in the  
clock rate adapter, which forces the Numerical Controlled Oscillator (NCO) to free-run based  
on the 10 MHz REFCKI input clock accuracy. When JFREE is active, JEN and JDIR select  
jitter attenuator direction.  
0 = normal (closed loop) CLAD/JAT operation  
1 = free run (open loop) NCO operation  
JDIR  
Select JAT DirectionApplicable only when the jitter attenuator is enabled (see JEN  
description). JAT elastic store is placed in either the receive or transmit direction, and JCLK is  
placed on RCKO or TCKO pin according to JDIR selection.  
0 = JAT in TX direction, JCLK output on TCKO  
1 = JAT in RX direction, JCLK output on RCKO  
N8370DSE  
Conexant  
3-11  
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