3.0 Registers
Bt8370/8375/8376
3.1 Address Map
Fully Integrated T1/E1 Framer and Line Interface
Table 3-1. Address Map (2 of 8)
Default Register Setting
Address
Acronym
(Hex)
R/W
Description
Bt8370
Bt8375
Bt8376
00C
00D
IER7
IER6
R/W
R/W
Alarm 1 Interrupt Enable
register
00
00
00
Alarm 2 Interrupt Enable
register
00
00
00
00E
00F
IER5
IER4
R/W
R/W
Error Interrupt Enable register
00
00
00
00
00
00
Count Overflow Interrupt
Enable register
010
011
012
013
014
IER3
IER2
IER1
IER0
LOOP
R/W
R/W
R/W
R/W
R/W
Timer Interrupt Enable
register
00
00
00
00
—
00
00
00
00
—
00
00
00
00
—
Data Link 1 Interrupt Enable
register
Data Link 2 Interrupt Enable
register
Pattern Interrupt Enable
register
Loopback Configuration
register
015
016
017
018
019
01A
01B
01C
DL3_TS
DL3_BIT
FSTAT
PIO
R/W
R/W
R
External Data Link Channel
External Data Link Bit
Offline Framer Status
Programmable Input/Output
Programmable Output Enable
Clock Input Mux
—
—
—
00
3F
00
00
00
—
—
—
00
3F
00
00
00
—
—
—
00
3F
00
00
00
R/W
R/W
R/W
R/W
R/W
POE
CMUX
TMUX
TEST
Test Mux Configuration
Test Configuration
3-2
Conexant
N8370DSE