AIS Baseband Processor
CMX910
2.
Block Diagram
AUXDAC1
AUXDAC0
DAC
RAM
10-bit
ADC
MUX
S/H
Aux ADC
Aux DACs
IOVDD
DVDD
AVSS
HDLC/
NRZI
decoder
IRX1P
IRX1N
I
Σ−Δ
ADC
GMSK
Slicer
Message
buffers
Rx1
FIFO
d
dt
φ
Q
QRX1P
QRX1N
Σ−Δ
ADC
FSK
demod.
Level Tracking
Rx Channel 1
BIAS
gen.
VBIAS
RDATA
SCLK
CDATA
CSN
HDLC/
NRZI
encoder
ITXP
ITXN
I
Σ−Δ
Message
buffer
Tx
FIFO
cos
sin
dt
DAC
Q
FSK
mod.
QTXP
QTXN
Σ−Δ
DAC
Tx Channel
CSXN
DVSS
AVSS
EXP5N
EXP4N
EXP3N
EXP2N
EXP1N
EXP0N
HDLC/
NRZI
decoder
IRX2P
IRX2N
I
Σ−Δ
GMSK
Slicer
Message
buffers
Rx2
FIFO
d
dt
φ
ADC
Q
QRX2P
QRX2N
Σ−Δ
ADC
FSK
demod.
Level Tracking
Rx Channel 2
FSK
retiming
FSK
FIFO
Analogue
2V5
regulator
Reset and
Power
Control
Slot and
Sample
Timer
Interrupt
Generator
AVDD
Device Enable Port
FSK Rx (Ext.)
Figure 1 CMX910 Block Diagram
© 2009 CML Microsystems Plc
4
D/910/6
CMLMICRO [ CML MICROCIRCUITS ]
