AIS Baseband Processor
CMX910
5.6.1 Receiver Registers
Rx1_FIFO register: 8-bit read only (data-streaming). C-BUS Address $30
Rx2_FIFO register: 8-bit read only (data-streaming). C-BUS Address $40
FSK_FIFO register: 8-bit read only (data-streaming). C-BUS Address $50
Independent 32 byte receive channel FIFOs, emptied on reset. Support C-BUS data streaming.
7
6
5
4
3
2
1
0
Bit:
$30:
$40:
$50:
Rx1 channel data byte
Rx2 channel data byte
FSK channel data byte
Rx1_FIFO and Rx2_FIFO are used to transfer AIS data to the µC from the Rx1 and Rx2 channels
respectively. FSK_FIFO is used to transfer FSK data to the µC from whichever channel is enabled
for DSC reception (either the Rx1 channel, Rx2 channel or the external FSK interface).
Rx1_FIFO_Threshold register: 8-bit write only.
Rx2_FIFO_Threshold register: 8-bit write only.
FSK_FIFO_Threshold register: 8-bit write only.
All registers set to $1F on reset.
C-BUS Address $31
C-BUS Address $41
C-BUS Address $51
7
6
5
4
3
2
1
0
Bit:
$31:
$41:
$51:
Reserved, set to 000
Reserved, set to 000
Reserved, set to 000
Rx1 FIFO threshold level
Rx2 FIFO threshold level
FSK FIFO threshold level
The receive FIFO threshold registers are used to set the level at which a “FIFO nearly full”
warning is triggered for each of the three receive channel FIFOs. If the number of bytes in a FIFO
is greater than the value in bits 4-0 of the associated threshold register then the FIFO Trigger flag
(bit 7 of the associated status register) will be set high. These flags can also be used to generate
interrupts. Bits 7-5 of the threshold registers should be set to 0.
Rx1_Status register: 16-bit read only.
Rx2_Status register: 16-bit read only.
FSK_Status register: 16-bit read only.
All bits cleared to 0 on reset.
C-BUS Address $32
C-BUS Address $42
C-BUS Address $52
15
14
13
12
11
10
9
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
Bit:
Rx1
Over- Under-
flow
Rx2
Over- Under-
flow flow
FSK FSK
Rx1
Rx1
FIFO
Trigger
Rx2
FIFO
Trigger
FSK
FIFO
$32:
Rx1 FIFO Fill Level
Rx2 FIFO Fill Level
FSK FIFO Fill Level
Rx1 State
flow
Rx2
$42:
$52:
0
0
0
0
0
0
0
0
Rx2 State
0
Over- Under-
flow
flow
Trigger
Rx1/Rx2/FSK_Status register b15: Overflow
These bits get set high if the µC does not read the associated FIFO quickly enough and allows it
to overflow, causing received data to be lost. Each overflow bit gets cleared as soon as the
associated status register is read.
© 2009 CML Microsystems Plc
33
D/910/6
CMLMICRO [ CML MICROCIRCUITS ]
