TDMA Digital Radio Processor
CMX7161
DC Parameters (continued)
Notes
Min.
Typ.
Max.
Unit
20
CLK
Input Logic ‘1’
Input Logic ‘0’
Input Current (Vin = DV
Input Current (Vin = DV
70%
–
–
–
–
–
–
–
30%
40
DV
DV
µA
µA
DD
DD
)
)
DD
–
40
SS
C-BUS Interface and Logic Inputs
Input Logic ‘1’
70%
–
1.0
–
–
–
–
–
–
DV
DD
Input Logic ‘0’
Input Leakage Current (Logic ‘1’ or ‘0’)
Input Capacitance
30%
1.0
7.5
DV
DD
11
µA
pF
C-BUS Interface and Logic Outputs
Output Logic ‘1’ (I = 2mA)
90%
–
-1.0
–
–
–
–
10%
1.0
DV
OH
DD
Output Logic ‘0’ (I = -5mA)
DV
OL
DD
“Off” State Leakage Current
11
21
µA
V
BIAS
–
–
±2%
50
–
–
AV
DD
k
Output Voltage Offset wrt AV /2 (I < 1A)
DD
OL
Output Impedance
20
21
Characteristics when driving the SYSCLKIN pin with an external clock source.
Applies when utilising V to provide a reference voltage to other parts of the
Notes:
BIAS
system. When using V
as a reference, V
must be buffered. V
must
BIAS
BIAS
BIAS
always be decoupled with a capacitor, as shown in Section 4 PCB Layout
Guidelines and Power Supply Decoupling.
2013 CML Microsystems Plc
Page 34
D/7161_FI-1.0/4
CMLMICRO [ CML MICROCIRCUITS ]
