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CS2000P-CZZR 参数 Datasheet PDF下载

CS2000P-CZZR图片预览
型号: CS2000P-CZZR
PDF下载: 下载PDF文件 查看货源
内容描述: 小数N分频时钟合成器与时钟乘法器 [Fractional-N Clock Synthesizer & Clock Multiplier]
分类和应用: 时钟
文件页数/大小: 30 页 / 568 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS2000-OTP  
5.4.6.1  
Manual Fractional-N Source Selection for the Frequency Synthesizer  
Manual selection of the fractional-N source for the frequency synthesizer can be done in one of two  
ways. The FracNSrc modal parameter can be set to the desired setting for each available configu-  
ration mode and then the Fractional N source is selected by the M1 and M0 pins. In order for this  
manual selection to work, the LockClk[1:0] modal parameter (even if unused) must be set to the  
same value as the modal ratio (Ratio 0 for Mode 0, Ratio 1 for Mode 1, etc.), see Section 5.4.6.2  
on page 17. Alternatively, the M2 pin in conjunction with the M2Config[2:0] global parameter can  
be set to control the fractional N source directly and thus override the FracNSrc modal parameter  
(see Section 5.7.2.5 on page 21 for details).  
Referenced Control  
Parameter Definition  
M[1:0] pins ............................ “M1 and M0 Mode Pin Functionality” on page 20  
LockClk[1:0].......................... “Lock Clock Ratio (LockClk[1:0])” section on page 24  
FracNSrc............................... “Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page 24  
M2Config[2:0] ....................... “M2 Pin Configuration (M2Config[2:0])” on page 26  
5.4.6.2  
Automatic Fractional-N Source Selection for the Frequency Synthesizer  
Automatic source selection allows for the selection of the frequency synthesizer’s fractional-N value  
to be made dependent on the presence of the CLK_IN signal. When CLK_IN is present the device  
will use the dynamic ratio generated from the Digital PLL and CLK_IN for Hybrid PLL Mode. When  
CLK_IN is not present, the device will use RefClk and the static ratio for Frequency Synthesizer  
23  
Mode. After losing CLK_IN, the CS2000-OTP will wait for 2 SysClk cycles before switching to Sy-  
sClk and re-acquiring lock, during which time the PLL is unlocked  
The modal ratio location (see Table 1 on page 10) should contain the desired CLK_OUT to RefClk  
ratio to be used when CLK_IN is not present. The User Defined Ratio pointed to by LockClk[1:0]  
should contain the desired CLK_OUT to CLK_IN ratio to be used when CLK_IN is present. Auto-  
matic source selection is enabled when the LockClk[1:0] modal parameter is set to a different User  
Defined Ratio from the modal ratio location.  
When automatic source selection is enabled, the FracNSrc modal parameter (used for manual  
clock selection) will be ignored.  
The automatic source selection feature can be disabled by setting the LockClk[1:0] modal param-  
eter to the modal ratio location. The FracNSrc modal parameter must then be used to select the  
desired clock used for the PLL’s frequency reference. The automatic source selection feature can  
also be disabled by using the M2 pin in conjunction with the M2Config[2:0] global parameter.  
Referenced Control  
Parameter Definition  
M[1:0] pins ............................ “M1 and M0 Mode Pin Functionality” on page 20  
LockClk[1:0].......................... “Lock Clock Ratio (LockClk[1:0])” section on page 24  
FracNSrc............................... “Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page 24  
M2Config[2:0] ....................... “M2 Pin Configuration (M2Config[2:0])” on page 26  
DS758PP1  
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