50S116T
SDRAM
Operating Timing Example, continued
Auto Precharge Timing (Write Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency = 2
( a ) burst length = 1
Command
Write
D0
AP
Act
tWR
tRP
DQ
( b ) burst length = 2
Command
Write
D0
AP
Act
AP
tWR
tRP
DQ
( c ) burst length = 4
Command
D1
D1
Write
D0
Act
D6
tWR
tRP
DQ
D2
D2
D3
D3
( d ) burst length = 8
Command
Write
D0
AP
Act
tWR
tRP
DQ
D1
AP
D4
D5
D7
(2) CAS Latency = 3
( a ) burst length = 1
Command
Write
D0
Act
tWR
tRP
DQ
( b ) burst length = 2
Command
Write
D0
Act
AP
tWR
tRP
DQ
( c ) burst length = 4
Command
D1
D1
D1
Write
D0
Act
D7
AP
D4
tWR
tRP
DQ
D2
D2
D3
D3
( d ) burst length = 8
Command
DQ
AP
Write
D0
Act
tWR
tRP
D5
D6
Note:
Write
AP
represents the Write with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Act
When the Auto precharge command is asserted, the period from Bank Activate
command to the start of internal precgarging must be at least tRAS(min).
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
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Rev 1.0 Aug.20,2002
Page 36 of 42
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