50S116T
SDRAM
Operating Timing Example, continued
Timing Chart of Burst Stop Cycle (Prechare Command)
(In the case of Burst Length = 8)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
( a ) CAS latency = 2
Commad
Read
PRCG
Q3
DQ
Q4
Q0
Q1
Q0
Q2
Q1
( b ) CAS latency = 3
Commad
DQ
PRCG
Q2
Read
Q4
Q3
(2) Write cycle
( a ) CAS latency = 2
Commad
PRCG
Write
WR
t
DQM
DQ
D4
D4
D0
D1
D2
D3
D3
( b ) CAS latency = 3
PRCG
Commad
Write
WR
t
DQM
DQ
D0
D1
D2
Note:
PRCG
represents the Precharge command
* All specs and applications shown above subject to change without prior notice.
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Rev 1.0 Aug.20,2002
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