50S116T
SDRAM
Operating Timing Example, continued
Bust Read and Single Write (Burst Lenght = 4, CAS Latency = 3)
(CLK = 100 MHz)
6
7
8
11 12 13
16 17 18
1
2
3
5
9
10
14 15
19
21
0
4
20
22 23
CLK
CS
RAS
CAS
WE
tRCD
BA
A10
RBa
A0-A9
CBz
RBa
CBv
CBw
CBx CBy
DQM
CKE
tAC
tAC
DQ
av0
av1
av3
aw0
ax0 ay0
az1
az2
az3
az0
av2
Q
Q
Q
Q
D
D
D
Q
Q
Q
Q
Read
Active
Single Write
Read
Bank #0
Bank #1
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3214525
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.0 Aug.20,2002
Page 33 of 42
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