50S116T
SDRAM
Operating Timing Example, continued
Timing Chart of Write-to-Read Cycle (In the case of Burst Length = 4)
1
2
3
4
5
6
7
8
9
10
11
0
(1) CAS Latency = 2
Write
Read
( a ) Command
DQM
D0
DQ
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
Read
Write
DQM
DQ
D1
Q3
D0
(2) CAS Latency = 3
( a ) Command
DQM
Read
Write
DQ
D0
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
DQM
Write
Read
D0
D1
Q3
DQ
Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10
11
(3) Read cycle
( a ) CAS latency =2
Command
Read
BST
DQ
Q4
Q3
Q0
Q1
Q0
Q2
Q1
Q3
BST
Q2
( b ) CAS latency = 3
Command
DQ
Read
Q4
(2) Write cycle
Command
BST
Write
D0
DQ
D1
D2
D3
D4
represents the Burst stop command
Note:
BST
* All specs and applications shown above subject to change without prior notice.
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Rev 1.0 Aug.20,2002
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