50S116T
SDRAM
Operating Timing Example, continued
Self Refresh Cycle
(CLK = 100 MHz)
6
7
8
11
12
13
16
17
18
1
2
3
5
9
10
14
15
19
21
0
4
20
22
23
CLK
CS
RAS
CAS
tRP
WE
BA
A10
A0-A9
DQM
tCKS
tCKS
tSB
CKE
DQ
tCKS
tRC
Self Refresh Cycle
No Operation Cycle
All Banks
Precharge
Self Refresh
Entry
Arbitrary Cycle
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3214525
Email: server@ceramate.com.tw
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Rev 1.0 Aug.20,2002
Page 32 of 42
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