50S116T
SDRAM
Operating Timing Example, continued
CKE/DQM Input Timing (Write Cycle)
1
CLK cycle No.
External
2
3
4
5
7
6
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D5
D6
DQM MASK
CKE MASK
( 1 )
2
3
4
5
7
1
6
CLK cycle No.
External
CLK
Internal
CKE
DQM
D1
D2
D3
D6
DQ
D5
DQM MASK
( 2 )
CKE MASK
1
2
3
4
5
6
7
CLK cycle No.
External
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D4
D5
D6
CKE MASK
( 3 )
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3214525
Email: server@ceramate.com.tw
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Rev 1.0 Aug.20,2002
Page 39 of 42
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