50S116T
SDRAM
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16
17
18
19
20 21
22
23
CLK
CS
tRC
tRC
tRC
RAS
tRAS
tRP
tRAS
tRAS
tRP
tRP
CAS
WE
BA
tRCD
tRCD
tRCD
A10
RAa
RAa
RAc
RAc
RBb
RBb
A0-A9
DQM
CAx
CBy
CAz
CKE
DQ
tAC
tAC
tAC
ax0
ax1
ax2
ax3
ax4
ax5
ax6
by0
by1
by4 by5
by6
by7
CZ0
tRRD
tRRD
Read
Active
Precharge
Active
Read
Precharge
Bank #0
Bank #1
Precharge
Active
Read
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3214525
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.0 Aug.20,2002
Page 23 of 42
Fax:886-3-3521052
CERAMATE [ CERAMATE TECHNICAL ]
