50S116T
SDRAM
11. OPERATING TIMING EXAMPLE
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
tRC
tRC
RAS
CAS
tRAS
tRP
tRAS
tRAS
tRP
tRP
tRAS
WE
BA
tRCD
tRCD
tRCD
tRCD
A10
RAa
RAa
RBb
RBb
RAc
RBd
RBd
RAe
CBx
A0-A9
DQM
RAc
CAy
RAe
CAw
CBz
CKE
DQ
tAC
tAC
tAC
tAC
bx3
cy2
bx1
aw0
aw2
aw3
bx0
bx2
cy1
cy3
aw1
cy0
tRRD
tRRD
tRRD
tRRD
Precharge
Read
Active
Read
Active
Bank #0
Bank #1
Read
Active
Precharge
Read
Precharge
Active
Active
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3214525
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.0 Aug.20,2002
Page 21 of 42
Fax:886-3-3521052
CERAMATE [ CERAMATE TECHNICAL ]
