50S116T
SDRAM
Timing Waveforms, continued
Control Timing of Input/Output Data
Input Data
(Word Mask)
CLK
tCMS
tCMH
tCMH
tCMS
DQM
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
DQ0 -15
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tCKS
CKE
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
DQ0 -15
Output Data
(Output Enable)
CLK
tCMS
tCMH
tCMS
tCMH
DQM
tAC
tHZ
tAC
tAC
tAC
tLZ
tOH
tOH
tOH
tOH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
OPEN
DQ0 -15
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tCKS
CKE
tAC
tAC
tAC
tAC
tOH
tOH
tOH
tOH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
DQ0 -15
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3214525
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.0 Aug.20,2002
Page 19 of 42
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CERAMATE [ CERAMATE TECHNICAL ]
