50S116T
SDRAM
Timing Waveforms, continued
Mode Reqister Set Cycle
tRSC
CLK
tCMS
tCMS
tCMS
tCMH
tCMH
tCMH
CS
RAS
CAS
WE
tCMS
tCMH
tAS
tAH
A0-A10
BA
Register
set data
next
command
Burst Length
A0
A1
A2
A3
A4
A5
A6
A2 A1 A0
A0
A0
Sequential
Interleave
Burst Length
0
0
0
0
1
1
1
1
A00
A00
A10
A10
A00
A00
A10
A10
0
1
0
1
0
1
0
1
1
2
4
1
2
4
8
A0
8
Addressing Mode
CAS Latency
Reserved
Reserved
A0
Full Page
A3
Addressing Mode
A0
0
Sequential
Interleave
A07 "0" (Test Mode)
A0
1
A8 "0"
A90
Reserved
CAS Latency
Reserved
A6 A50 A4
0
0
0
0
1
A00
0
1
1
0
0
1
0
1
0
WriteAM0 ode
A0
Reserved
"0"
"0"
2
3
A10
BA
ResAe0rved
Reserved
A9
0
1
Single Write Mode
Burst read and Burst write
Burst read and single write
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3214525
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.0 Aug.20,2002
Page 20 of 42
Fax:886-3-3521052
CERAMATE [ CERAMATE TECHNICAL ]
