50S116T
SDRAM
Operating Timing Example, continued
Interleaved Bank Write (Burst Length = 8)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21
22
23
CLK
CS
tRC
RAS
CAS
WE
tRAS
tRAS
tRP
tRAS
tRP
tRCD
tRCD
tRCD
BA
RBb
RAc
RAc
A10
RAa
RAa
CAx
RBb
CBy
CAz
A0-A9
DQM
CKE
DQ
ax0
ax1
ax4
ax5
ax6
ax7 by0
by1
by2
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
tRRD
tRRD
Active
Write
Precharge
Active
Write
Bank #0
Bank #1
Active
Write
Precharge
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3214525
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.0 Aug.20,2002
Page 25 of 42
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