Data Sheet
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Logic Inputs (CMOS)
VOVDD ≥ 3.0V
2
V
V
VIH
VIL
High Level Input Voltage
VOVDD = 1.7V – 3.0V
VOVDD ≥ 3.0V
0.8 • VOVDD
0
0
0.8
0.2 • VOVDD
±10
V
Low Level Input Voltage
VOVDD = 1.7V – 3.0V
V
IIH
IIL
CI
High Level Input Leakage Current
Low Level Input Leakage Current
Input Capacitance
µA
µA
pF
±10
3
Data Outputs (LVDS)
Compliance
LVDS
VOUT
VCM
Differential Output Voltage
Output Common Mode Voltage
Output Coding
350
1.2
mV
V
Default/Optional
Offset Binary/2‘s Complement
Timing Characteristics
TAP
Aperture Delay
0.8
ns
ps
εRMS
Aperture Jitter
<0.5
clock
cycles
Start up time from Power Down to Active
Mode. References have reached 99% of final
value. (See section Clock Frequency)
260
992
TPD
Start up Time from Power Down
15
0.5
1
µs
TSLP
TOVR
TLAT
Startup Time from Sleep
Out Of Range Recovery Time
Pipeline Delay
Start up time from Sleep Mode to Active Mode
µs
clk cycles
clk cycles
14
LVDS Output Timing Characterisctics
tdata
LCLK to Data Delay Time
Excluding programmable phase shift
250
ps
ns
7 • TLVDS
+2.6
7 • TLVDS
+3.5
7 • TLVDS
+4.2
tPROP
Clock Propogation Delay
% LCLK
cycle
LVDS Bit-Clock Duty-Cycle
Frame clock cycle-to-cycle jitter
Data Rise- and Fall Time
45
55
% LCLK
cycle
2.5
TEDGE
Calculated from 20% to 80%
Calculated from 20% to 80%
0.4
0.4
ns
ns
TCLKEDGE
Clock Rise- and Fall Time
Note:
(1) Signal applied to 7 channels (FIN0). Measurement taken on one channel with full scale at FIN1. FIN1 = 8MHz, FIN0 = 9.9MHz
(2) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
and resulting switching noise at a minimum.
©2009 CADEKA Microcircuits LLC
www.cadeka.com
14
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
