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SMJ44C251B-12HJM 参数 Datasheet PDF下载

SMJ44C251B-12HJM图片预览
型号: SMJ44C251B-12HJM
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ×4 VRAM 256K ×4的DRAM 512K ×4的SAM [256K X 4 VRAM 256K x 4 DRAM with 512K x 4 SAM]
分类和应用: 内存集成电路动态存储器
文件页数/大小: 57 页 / 1255 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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VRAM  
SMJ44C251B  
MT42C4256  
Austin Semiconductor, Inc.  
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES  
OF SUPPLY VOLTAGESAND OPERATING FREE-AIR TEMPERATURE  
(UNLESS OTHERWISE NOTED)  
PARAMETER  
SYM  
CONDITIONS  
MIN  
MAX  
UNIT  
High-level output voltage  
VOH  
IOH = -5mA  
2.4  
V
Low-level output voltage1  
VOL  
II  
IOL = 4.2mA  
0.4  
±10  
±10  
V
VCC = 5V, VI = 0V to 5.8V,  
All others open  
Input leakage current  
µA  
µA  
Output leakage current2  
IO  
VCC = 5.5V, VO = 0V to VCC  
-10  
-12  
SAM  
CONDITIONS  
3
SYM  
MIN MAX MIN MAX UNITS  
PARAMETER  
PORT  
Operating current  
I
t
t
and t = MIN Standby  
c(W)  
100  
110  
15  
90  
100  
15  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
CC1  
c(rd)  
Operating current  
I
t
= MIN  
Active  
Standby  
Active  
CC1A  
c(SC)  
Standby current  
I
All clocks = V  
CC  
CC2  
Standby current  
I
t
= MIN  
35  
35  
CC2A  
c(SC)  
RAS\-only refresh current  
RAS\-only refresh current  
Page-mode current  
Page-mode current  
CAS\-before-RAS\ current  
CAS\-before-RAS\ current  
Data-transfer current  
Data-transfer current  
I
and t = MIN Standby  
c(W)  
100  
110  
65  
90  
CC3  
c(rd)  
I
t
= MIN  
Active  
Standby  
Active  
100  
60  
CC3A  
c(SC)  
I
t
= MIN  
= MIN  
CC4  
c(P)  
I
t
70  
65  
CC4A  
c(SC)  
I
t
t
and t = MIN Standby  
c(W)  
90  
80  
CC5  
c(rd)  
I
t
= MIN  
Active  
and t = MIN Standby  
c(W)  
110  
100  
110  
100  
90  
CC5A  
c(SC)  
I
CC6  
c(rd)  
I
t
= MIN  
Active  
100  
CC6A  
c(SC)  
NOTES:  
1. The SMJ44C251B may exhibit simultaneous switching noise as described in the Texas Instruments Advanced CMOS Logic Designers Handbook.  
This phenomenon is exhibited on the DQ terminals when the SDQ terminals are switched and on the SDQ terminals when the DQ terminals are  
switched. This may cause VOL and VOH to exceed the data-book limit for a short period of time, depending upon output loading and temperature. Care  
should be taken to provide proper termination, decoupling, and layout of the device to minimize simultaneous switching effects.  
2. SE\ is disabled for SDQ output leakage tests.  
3. ICC (standby) denotes that the SAM port is inactive (standby) and the DRAM port is active (except for ICC2).  
ICCA (active) denotes that the SAM port is active and the DRAM port is active (except for ICC2).  
ICC is measured with no load on DQ or SDQ.  
4. For conditions shown as MIN/ MAX, use the appropriate value specified in the timing requirements.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
SMJ44C251B/MT42C4256  
Rev. 0.1 12/03  
17  
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