SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
A fixed-length READ burst may be followed by, or desired of a longer burst. Following the PRECHARGE
truncated with, a PRECHARGE command to the same bank command, a subsequent command to the same bank cannot be
(provided that AUTO PRECHARGE was not activated), and a
full-page burst maybe truncated with a PRECHARGE command
to the same bank. The PRECHARGE command should be is-
sued x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS latency;
data element n + 3 is either the last of a burst of four or the last
issued until tRP is met. Note that part of the row precharge time
is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the optimum
time (as described above) provides the same operation that
would result from the same fixed-length burst
T6
T7
T0
T1
T2
T3
T4
T5
CLK
t
RP
NOP
READ
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
COMMAND
X = 1 cycles
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
ADDRESS
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 2
T6
T7
T0
T1
T2
T3
T4
T5
CLK
t
RP
READ
NOP
PRECHARGE
NOP
NOP
NOP
NOP
COMMAND
ACTIVE
X = 2 cycles
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
ADDRESS
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 3
NOTE: DQM is LOW.
DON’T CARE
Figure 11
READ TO PRECHARGE
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 1.5 10/01
17
AUSTIN [ AUSTIN SEMICONDUCTOR ]
