SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
Data from any READ burst may be truncated with a
T0
T1
T2
T3
T4
subsequent WRITE command, and data from a fixed-length
READ burst may be immediately followed by data from a WRITE
command (subject to bus turnaround limitations). The WRITE
burst may be initiated on the clock edge immediately following
the last (or last desired) data element from the READ burst,
provided that I/O contention can be avoided. In a given
system design, there may be a possibility that the device
driving the input data will go Low-Z before the SDRAM DQs
go High-Z. In this case, at least a single-cycle delay should
occur between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in
Figures 9 and 10. The DQM signal must be asserted (HIGH) at
least two clocks prior to the WRITE command (DQM latency is
two clocks for output buffers) to suppress data-out from the
READ. Once the WRITE command is registered, the DQs will
go High-Z (or remain High-Z), regardless of the state of the
DQM signal. The DQM signal must be de-asserted prior to the
WRITE command (DQM latency is zero clocks for input
buffers) to ensure that the written data is not masked. Figure 9
shows the case where the clock frequency allows for bus
contention to be avoided without adding a NOP cycle, and
Figure 10 shows the case where the additional NOP is needed.
CLK
DQM
READ
NOP
NOP
COMMAND
ADDRESS
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
CK
t
HZ
DOUT
n
DIN b
DQ
t
DS
NOTE: A CAS latency of three is used for illustration. The READ command may be to any
bank, and the WRITE command may be to any bank. If a CAS latency of one is used, the
DQM is not required.
Figure 9
READ TO WRITE
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DQ
DOUT
n
DIN b
t
DS
NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank,
and the WRITE command may be to any bank.
DON’T CARE
Figure 10
READ TO WRITE WITH EXTRA
CLOCK CYCLE
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 1.5 10/01
16
AUSTIN [ AUSTIN SEMICONDUCTOR ]
