SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
Data for any WRITE burst may be truncated with a WRITE burst, the DQM signal must be used to mask input data
subsequent READ command, and data for a fixed-length WRITE for the clock edge prior to, and the clock edge coincident with,
burst may be immediately followed by a subsequent READ the PRECHARGE command. An example is shown in Figure 18.
command. Once the READ command is registered, the data Data n + 1 is either the last of a burst of two or the last desired
inputs will be ignored, and WRITEs will not be executed. An of a longer burst. Following the PRECHARGE command, a
example is shown in Figure 17. Data n+1 is either the last of a subsequent command to the same bank cannot be issued until
burst of two or the last desired of a longer burst.
tRP is met.
In the case of a fixed-length burst being executed to
Data for a fixed-length WRITE burst may be followed
by, or truncated with, a PRECHARGE command to the same
bank (provided that AUTO PRECHARGE was not activated),
and a full-page WRITE burst may be truncated with a
PRECHARGE command to the same bank. The PRECHARGE
completion, a PRECHARGE command issued at the optimum
time (as described above) provides the same operation that
would result from the same fixed-length burst with AUTO
PRECHARGE. The disadvantage of the PRECHARGE command
is that it requires that the command and address buses be
available at the appropriate time to issue the command; the
advantage of the PRECHARGE command is that it can be used
t
command should be issued WR after the clock edge at which
the last desired input data element is registered. The Auto
Precharge mode requires a tWR of at least one clock plus time
(8ns), regardless of frequency. In addition, when truncating a to truncate fixed-length or full-page bursts.
T0
T1
T2
T3
T0
T1
T2
T3
T4
T5
T6
CLK
CLK
tWR= 2 CLK (“A2 version”)
WRITE
WRITE
WRITE
COMMAND
WRITE
DQM
t
RP
BANK,
COL n
BANK,
COL m
BANK,
COL a
BANK,
COL x
ADDRESS
DQ
NOP
PRECHARGE
NOP
NOP
ACTIVE
NOP
WRITE
COMMAND
DIN
n
DIN a
DIN
x
DIN m
BANK
a,
COL n
BANK
(a or all)
BANK
a,
ROW
ADDRESS
DQ
t
WR
NOTE: Each WRITE command may be to any bank. DQM is
DIN
n
DIN n+1
LOW.
Figure 16
NOTE: DQM coulc remain LOW in this example if the WRITE burst is a fixed length
RANDOM WRITE CYCLES
of 2.
DON’T CARE
Figure 18
WRITE TO PRECHARGE
T0
T1
T2
T3
T4
T5
CLK
COMMAND
WRITE
NOP
NOP
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT
b
DOUT b+1
DIN
n
DIN n+1
NOTE: The WRITE command may be to any bank, and the READ command may be to
any bank. DQM is LOW. CAS latency = 2 for illustration.
Figure 17
WRITE TO READ
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 1.5 10/01
20
AUSTIN [ AUSTIN SEMICONDUCTOR ]
