SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
T0
T1
T2
T3
T4
T5
CLK
READ
READ
READ
READ
NOP
NOP
COMMAND
BANK,
COL n
BANK,
COL x
BANK,
COL a
BANK,
COL m
ADDRESS
DQ
DOUT
a
DOUT
n
DOUT
x
DOUT
m
CAS Latency = 2
T6
T0
T1
T2
T3
T4
T5
CLK
READ
NOP
READ
READ
READ
NOP
NOP
COMMAND
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
ADDRESS
DQ
DOUT
a
DOUT
n
DOUT
x
DOUT
m
CAS Latency = 3
DON’T CARE
NOTE: Each READ command may be to either bank. DQM is LOW.
Figure 8
RANDOM READ ACCESSES
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 1.5 10/01
15