欢迎访问ic37.com |
会员登录 免费注册
发布采购

AS4SD4M16DG-10/XT 参数 Datasheet PDF下载

AS4SD4M16DG-10/XT图片预览
型号: AS4SD4M16DG-10/XT
PDF下载: 下载PDF文件 查看货源
内容描述: 4梅格×16 SDRAM同步动态随机存取存储 [4 Meg x 16 SDRAM Synchronous DRAM Memory]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 50 页 / 1139 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
 浏览型号AS4SD4M16DG-10/XT的Datasheet PDF文件第10页浏览型号AS4SD4M16DG-10/XT的Datasheet PDF文件第11页浏览型号AS4SD4M16DG-10/XT的Datasheet PDF文件第12页浏览型号AS4SD4M16DG-10/XT的Datasheet PDF文件第13页浏览型号AS4SD4M16DG-10/XT的Datasheet PDF文件第15页浏览型号AS4SD4M16DG-10/XT的Datasheet PDF文件第16页浏览型号AS4SD4M16DG-10/XT的Datasheet PDF文件第17页浏览型号AS4SD4M16DG-10/XT的Datasheet PDF文件第18页  
SDRAM  
AS4SD4M16  
Austin Semiconductor, Inc.  
This is shown in Figure 7 for CAS latencies of two and three;  
data element n + 3 is either the last of a burst of four or the last  
desired of a longer burst. The 64Mb SDRAM uses a pipelined  
architecture and therefore does not require the 2n rule  
associated with a prefetch architecture. A READ command can  
be initiated on any clock cycle following a previous READ  
command. Full-speed random read accesses can be performed  
to the same bank, as shown in Figure 8, or each subsequent  
READ may be performed to a different bank.  
T6  
T0  
T1  
T2  
T3  
T4  
T5  
CLK  
NOP  
NOP  
NOP  
NOP  
NOP  
READ  
READ  
COMMAND  
X=1 cycle  
BANK,  
COL n  
BANK,  
COL b  
ADDRESS  
DQ  
DOUT  
n+2  
DOUT  
n+1  
DOUT  
n
DOUT  
n+3  
DOUT  
b
CAS Latency = 2  
T7  
T6  
T0  
T1  
T2  
T3  
T4  
T5  
CLK  
NOP  
NOP  
READ  
NOP  
NOP  
READ  
NOP  
NOP  
COMMAND  
X=2 cycle  
BANK,  
COL n  
BANK,  
COL b  
ADDRESS  
DQ  
DOUT  
n+2  
DOUT  
n+1  
DOUT  
n
DOUT  
n+3  
DOUT  
b
CAS Latency = 3  
NOTE: Each READ command may be to either bank. DQM is LOW.  
DON’T CARE  
Figure 7  
CONSECUTIVE READ BURSTS  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS4SD4M16  
Rev. 1.5 10/01  
14  
 复制成功!