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AS4DDR232M64PBGR-5/IT 参数 Datasheet PDF下载

AS4DDR232M64PBGR-5/IT图片预览
型号: AS4DDR232M64PBGR-5/IT
PDF下载: 下载PDF文件 查看货源
内容描述: 32Mx64 DDR2 SDRAM集成塑封微电路 [32Mx64 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 内存集成电路动态存储器双倍数据速率
文件页数/大小: 28 页 / 363 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
2.1 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR232M64PBG  
TABLE 2 - BURST DEFINITION  
Order of Accesses Within a Burst  
DLL RESET  
Burst  
Starting Column  
Address  
Length  
Type = Sequential  
Type = Interleaved  
DLL RESET is defined by bit M8, as shown in Figure 5.  
Programming bit M8 to “1” will activate the DLL RESET  
function. Bit M8 is self-clearing, meaning it returns back  
to a value of ¡°0¡ after the DLL RESET function has been  
issued.  
A1 A0  
0
0
1
1
0
1
0
1
0-1-2-3  
1-2-3-0  
2-3-0-1  
3-0-1-2  
0-1-2-3  
1-0-3-2  
2-3-0-1  
3-2-1-0  
4
Anytime the DLL RESET function is used, 200 clock cycles  
must occur before a READ command can be issued to allow  
time for the internal clock to be synchronized with the external  
clock. Failing to wait for synchronization to occur may result  
A2 A1 A0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7  
1-2-3-4-5-6-7-0  
2-3-4-5-6-7-0-1  
3-4-5-6-7-0-1-2  
4-5-6-7-0-1-2-3  
5-6-7-0-1-2-3-4  
6-7-0-1-2-3-4-5  
7-0-1-2-3-4-5-6  
0-1-2-3-4-5-6-7  
1-0-3-2-5-4-7-6  
2-3-0-1-6-7-4-5  
3-2-1-0-7-6-5-4  
4-5-6-7-0-1-2-3  
5-4-7-6-1-0-3-2  
6-7-4-5-2-3-0-1  
7-6-5-4-3-2-1-0  
t
t
in a violation of the Aꢁ or DQSꢁK parameters.  
8
WRITE RECOVERY  
Write recovery (WR) time is defined by bits M9-M11, as shown  
in Figure 5. The WR register is used by the DDR2 SDRAM  
during WRITE with auto precharge operation. During WRITE  
with auto precharge operation, the DDR2 SDRAM delays  
the internal auto precharge operation by WR clocks  
(programmed in bits M9-M11) from the last data burst.  
NOTES:  
1. For a burst length of two, A1-Ai select two-data-element block;  
A0 selects the starting column within the block.  
2. For a burst length of four, A2-Ai select four-data-element block;  
A0-1 select the starting column within the block.  
3. For a burst length of eight, A3-Ai select eight-data-element block;  
A0-2 select the starting column within the block.  
4. Whenever a boundary of the block is reached within a given  
sequence above, the following access wraps within the block.  
WR values of 2, 3, 4, 5, or 6 clocks may be used for  
programming bits M9-M11. The user is required to program  
the value of WR, which is calculated by dividing tWR (in ns)  
by tꢁK (in ns) and rounding up a non integer value to the next  
integer; WR [cycles] = WR [ns] ꢀ ꢁK [ns]. Reserved states  
should not be used as unknown operation or incompatibility  
with future versions may result.  
t
t
OPERATING MODE  
The normal operating mode is selected by issuing a  
command with bit M7 set to ¡°0,¡ and all other bits set to  
the desired values, as shown in Figure 5. When bit M7 is  
“1,” no other bits of the mode register are programmed.  
Programming bit M7 to ¡°1¡ places the DDR2 SDRAM into a  
test mode that is only used by the manufacturer and should  
not be used. No operation or functionality is guaranteed  
if M7 bit is “1.”  
POWER-DOWN MODE  
Active power-down (PD) mode is defined by bit M12, as  
shown in Figure 5. PD mode allows the user to determine  
the active power-down mode, which determines  
performance versus power savings. PD mode bit M12 does  
not apply to precharge PD mode.  
When bit M12 = 0, standard active PD mode or “fast-exit”  
active PD mode is enabled. The XARD parameter is used  
t
for fast-exit active PD exit timing. The DLL is expected to be  
enabled and running during this mode.  
When bit M12 = 1, a lower-power active PD mode or “slowexit”  
t
active PD mode is enabled. The XARD parameter is used  
for slow-exit active PD exit timing. The DLL can be enabled,  
but “frozen” during active PD mode since the exit-to-READ  
command timing is relaxed. The power difference expected  
between PD normal and PD low-power mode is defined in  
the Iꢁꢁ table.  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR232M64PBG  
Rev. 1.3 6/09  
9
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