iPEM
2.1 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR232M64PBG
FIGURE 4 - POWER-UP AND INITIALIZATION
Notes appear on page 7
VCC
V
CC
Q
1
t
1
VTD
V
TT
V
REF
Tk0
Tl0
Tm0
Tg0
Th0
Ti0
Tj0
Te0
Tf0
Tc0
Td0
Tb0
T0
Ta0
t
CK
CK#
CK
t
t
CL
CL
See
note
3
SSTL_18
LVCMOS
8
8
LOW LEVEL
CKE LOW LEVEL
ODT
3
2
COMMAND
REF
LM
LM
VALID
LM
LM
LM
PRE
PRE
LM
LM
REF
NOP
7
DM
9
ADDRESS
CODE
CODE
CODE
A10 = 1
CODE
CODE
CODE
CODE
A10 = 1
VALID
High-Z
High-Z
7
DQS
7
DQ
High-Z
RTT
t
t
t
t
t
t
t
t
t
MRD
T = 200μs (MIN)
Power-up:
CC and stable
clock (CK, CK#)
t
MRD
t
T = 400ns
(MIN)
RPA
MRD
MRD
MRD
MRD
EMR with
RPA
5
RFC
RFC
MRD
Seenote4
V
DLL ENABLE
EMR(2)
EMR(3)
MR w/o
EMR with
DLL RESET OCD Default
EMR with
10
11
OCD Exit
Normal
Operation
3
200 cycles of CK
MR with
DLL RESET
Indicates a break in
time scale
DON’T CARE
Austin Semiconductor, Inc.
● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com
AS4DDR232M64PBG
Rev. 1.3 6/09
6
AUSTIN [ AUSTIN SEMICONDUCTOR ]
