iPEM
2.1 Gb SDRAM-DDR2
Austin Semiconductor, Inc.
AS4DDR232M64PBG
POSTED CAS ADDITIVE LATENCY (AL)
Posted ꢁAS additive latency (AL) is supported to make the
command and data bus efficient for sustainable bandwidths
in DDR2 SDRAM. Bits E3–E5 define the value of AL, as
shown in Figure 7. Bits E3–E5 allow the user to program
the DDR2 SDRAM with an inverse AL of 0, 1, 2, 3, or 4
clocks. Reserved states should not be used as unknown
operation or incompatibility with future versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE
command to be issued prior to tRꢁD (MIN) with the
requirement that AL d” tRꢁD (MIN). A typical application using
this feature would set AL = tRꢁD (MIN) - 1x tꢁK. The READ or
WRITE command is held for the time of the AL before it is
issued internally to the DDR2 SDRAM device. RL is controlled
by the sum of AL and ꢁL; RL = AL+ꢁL. Write latency (WL) is
equal to RL minus one clock; WL = AL + ꢁL - 1 x tꢁK.
FIGURE 8 - EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Extended Mode
Register (Ex)
15 14 13 12 11 10
EMR2
9
8
7
6
5
4
3
2
1
0
01 01 01
01 01 01 01 01 01 01 01 01 01 01
Mode Register Definition
M15 M14
High Temperature Self Refresh rate enable
Commer cial-Temperature default
Industrial-Temperature option;
use if TCexceeds 85°C
E7
0
0
1
0
1
Mode Register (MR)
0
0
1
1
Extended Mode Register (EMR)
Extended Mode Register (EMR2)
Extended Mode Register (EMR3)
1
Note: 1. E13 (A13)-E0(A0) are reserved for future use and must be programmed to
"0." A13 is not used in this device.
Austin Semiconductor, Inc.
● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com
AS4DDR232M64PBG
Rev. 1.3 6/09
13
AUSTIN [ AUSTIN SEMICONDUCTOR ]
